Field-Programmable Gate Arrays

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cmos delay vs temperature

I found one old Fairchild appnote that has some numbers https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/CMOS_D...
3 comments posted 9yrs
posted by jjlarkinxyxy
3 comments posted 9yrs posted by jjlarkinxyxy

Intel (Altera) announces Cyclone-10

It looks like Intel has learned to count from Microsoft. The previous generation of Cyclone was Cyclone-5. https://www.a...
13 comments posted 9yrs
posted by gabor
13 comments posted 9yrs posted by gabor

All-real FFT for FPGA

So, there are algorithms out there to perform an FFT on real data, that save (I think) roughly 2x the calculations of F...
34 comments posted 9yrs
posted by seemywebsite
34 comments posted 9yrs posted by seemywebsite

Go to church

That still small voice you hear on the inside, the one drawing you from within, reminding you of the things you should...
0 comments posted 9yrs
posted by rick.c.hodgin
0 comments posted 9yrs posted by rick.c.hodgin

Hardware floating point?

So, just doing a brief search, it looks like Altera is touting a floating point slice in at least one of their lines. I...
25 comments posted 9yrs
posted by seemywebsite
25 comments posted 9yrs posted by seemywebsite

Anyone use 1's compliment or signed magnitude?

This is kind of a survey; I need some perspective (possibly historical) Are there any digital systems that you know of...
18 comments posted 9yrs
posted by seemywebsite
18 comments posted 9yrs posted by seemywebsite

VHDL Editors (esp. V3S)

As X and A's integrated editors are more or less limited, I guess many peop le will looking for better alternatives. Th...
14 comments posted 9yrs
posted by thomas.entner99
14 comments posted 9yrs posted by thomas.entner99

VHDL, how to convert sensor data to Q15

Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign...
13 comments posted 9yrs
posted by abirov
13 comments posted 9yrs posted by abirov

Terminating an Aurora link in a PC

Hi I have two devices communicating via an Aurora link (single lane, full duplex) over SFP + optical cables. I need to...
4 comments posted 9yrs
posted by karl.robinsod
4 comments posted 9yrs posted by karl.robinsod

VHDL I2c burst read

Dear All, please help with VHDL, i connected MPU6050 to my FPGA board. I used www.eewiki.com tutorial, can anybody exlp...
6 comments posted 9yrs
posted by abirov
6 comments posted 9yrs posted by abirov

True Random Number Gen in Virtex 7

Has anybody tried to build a true random number generator from Catalin Baetoniu's paper? http://forums.xilinx.com/xlnx/...
3 comments posted 9yrs
posted by kevin.neilson
3 comments posted 9yrs posted by kevin.neilson

Lattice Semiconductor $99 promo on several items

If you're not on their mailing list, Lattice Semiconductor has some items on sale through January 27, 2017 or as suppli...
0 comments posted 9yrs
posted by rick.c.hodgin
0 comments posted 9yrs posted by rick.c.hodgin