Address sensitive process, Xilinx virtex2pro

Add this:

if( Bus2ip_clk'event and Bus2ip_Clk='1') then

end if ;

Naah, This is better.

if rising_edge(Bus2ip_Clk) then

end if ;

HTH., Syms.

Taking a guess, it looks like you are using Xilinx, and taking another guess, you may have created your core using the Xilinx Create Peripheral Wizard.

If you did, one thing to look out for is the USER_HIGHADDR. Depending on what options you choose int the Peripheral Wizard, in the core wrapper file the USER_HIGHADDR could be being set with the following line (syntax purposefully abbreviated).

USER_HIGHADDR : stl := C_BASEADDR or X"000000FF";

Which has the annoying effect of only allowing 256 byte addresses. If you are trying to read an address within your core above xFF, the IPIF returns 0 for you.

In my cores, when I see this I always just change this line to read USER_HIGHADDR : stl := C_HIGHADDR;

Hope this helps.

Erik

means to me:

Yes, Symon, that's shorter.

Have you thought about what happens to bus2ip_data before the magic address is hit? What about after it has been hit?

What else (if anything) is driving bus2ip_data? If nothing, bus2ip_data will be (others => 'U') before, and X"FF00FF00" after, forevermore.

If something else is driving data, then a (others => 'X') will almost certainly result.

Andy

No, I had not thought of it. I was just correcting the obvious lack of a clk if-then and hopefully explaining why he got zeroes. Perhaps, there is another driver.

Sorry Brad, my reply was meant for the OP instead of you.

Andy

Hi Brad, There's a little bit more to it than that. For synthesis, the two forms are identical, I think. However, for simulation, IIRC, the rising_edge form is 'better' because it only triggers when the clock changes from '0' to '1'. The other form triggers when the signal changes from anything, e.g. 'Z' or 'U', to '1'.

But it is shorter too! :-) Cheers, Syms.