Hi, I have a question on Synplicity synthesis / FPGA synthesis.
Is there a way to give in the `defines from the command lines in synplicity synthesis .. something like
add_file -verilog +define ..... filename.v
I am not sure if it's +define or something else, so thought of giving this querty to the group. I have researched this stuff in the user and reference manual but couldn't find a link.
Any kinda help is appreciated.
Thanks!