Physical Design Contribution to FPGA/CPLD success

They wouldn't have been programmable.

-- Mike Treseler

Originally, FPGA had to overcome the "to small, too slow, too expensive" criticism, and had to use every possible circuit trick to become more efficient. Replacing ASICs came later, when size, speed and cost had become competitive with some ASIC applications. If we had not pulled all the stops to become efficient, we might now be a footnote in history,,, Horribile dictu. Peter Alfke

Meant also to Peter:

Mike, either I did miss your irony or you did get me wrong: Of course one could implement an FPGA with vanilla CMOS latches and gates, build your configuration registers with standard latches, build the LUT-readout multiplexer with standard gates, build the routing with combinational multiplexers and standard latches. I guess, the Algotronix (later Xilinx 6200) devices would have been more friendly for this, than the Xilinx 2000 devices, but it could be done. You would just need way more transistors.

My assumption was that if Xilinx/AMD/Lattice & Co. would have done it this way, the capacity/cost would have been so poor that the FPGA business had never taken off, or at least much weaker and later. Peter kind of confirmed that assumption, thanks.

Andreas

Neither, although I suppose that everything I say and do is ironic at some level.

The expensive part of an ASIC isn't the gates and flops, it's the wires. The big idea that eventually made FPGAs successfully is programmable wires. Wherever I am on the chip I can pick up a low skew clock with no effort on my part. That's the special sauce.

-- Mike Treseler

successful

Next big idea: A smart spell checker.

I think you're confusing the product of an ASIC and an FPGA. ASICs are limited to "standard" cell devices, because the tools have to be easily applicable (and verifiable!) to a wide variety of situations.

An FPGA (the virgin part, not the programmed application) is more like a high-end processor, with much larger volumes to support dedicated designs using "non-standard" features. I'm sure you'd find similar tricks in any large, high-volume, fully custom, digital IC.

No major processor would survive in the market without similar tricks either.

Andy

Similar to Fortran, which was competing with hand-coded assembler and had to produce really good code.

(snip, someone wrote)

I am sure this used to be true, but I would expect it to be less true today. In the early microprocessor days, every last transistor had to be counted. Intel used dynamic logic for many processors, including the 8080 and 8086. (That results in a minimum clock frequency.) Pass transistors were also common at the time.

As the supply voltage gets lower, it is more difficult to use pass transistor.

-- glen

It's not clear what you mean by 'vanilla CMOS gates and latches' ?

CPLDs were quite different from FPGAs in structure, and Philips were the leaders in 'true CMOS' CPLDs, which now sees Atmel/Lattice/Xilinx(via Philips) offering CMOS CPLDs.

FPGAs have always needed MUX elements (your pass-transistor) as they have always had a routing element.

If you again look back at CPLDs, you will see above a certain size, they also have recently moved to MUX/Tiled designs - so that gives you the answer. Below a certain size, 'vanilla CMOS' makes sense, and above that level, you need MUX's to stay efficent.

A factor in that branch, will also be the Software experience that exists in FPGA design tools. Whilst there may possibly have been another middle structure, the mature design flows in the FPGA camp, made that jump natural for CPLDs.

-jg

(snip)

You can make a MUX out of pass transistors, or NAND gates.

Pass transistors have the advantage of being bidirectional. Advantage in early FPGAs (for routing), but as I understand it maybe not anymore.

It would likely take a lot more transistors in NAND gates.

-- glen