Hi,
Does anyone know which algorithm or scheme is used by Quartus to compress FPGA configuration files such as SOF or RBF (raw binary file)?
Thanks, Jason
Hi,
Does anyone know which algorithm or scheme is used by Quartus to compress FPGA configuration files such as SOF or RBF (raw binary file)?
Thanks, Jason
Even if the method were public:
I'll try to address your questions, but I get the feeling you don't have the answer I'm looking for.
Ok, then lets narrow it down to Cyclone devices.
Enough to bother asking here ;)
Given the amount of lossless compression schemes out there, I doubt Altera would want to reinvent the wheel. But I'm hoping someone has already gone through the exercise of figuring out the formatting - it would save me some time.
Regards, Jason
It's difficult to express any enthusiasm when your interest appears to be academic. Quartus can compress a .SOF file for you. The device can unravel the result. Why would you want to do either of these yourself?
If you tell us what your real problem is, it can be better addressed. Otherwise, some kind person will make what they think is a helpful contribution, to which you will then reply "Ah, but what I really want is...". So, why the secrecy?
The only way to know the algorithm reliably is if Altera publish it. Maybe you can take a bunch of example files (maybe a million of them) and work out a conversion algorithm that works for all those files, but that doesn't mean it will work for any possible file. There is an infinite number of algorithms, all of which will work with the example files but none of which are correct. So, even if someone tells you that they have "figured it out", you can't rely on what they tell you.
So, you need to ask Altera. If their reply is "we don't publish that information", you're stuck.
Mike
I don't know what Altera does, but I would suppose it's pretty similar to what Xilinx does, and what they do is not a real compression at all.
The configuration is written to the fpga in frames, and when some logic is not used, you get unused, empty frames. All the "compression" really does is not to put those empty frames in the bitstream, that's it, no Huffman-coding or Lempel-Ziv or whatever. That's why the FPGA can "decompress" it on-the-fly without too much of a hassle.
I doubt Altera does it a lot differently...
HTH, Sean
-- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...
Thanks Sean,
Makes a lot of sense. I'll look into that.
Jason
FYI:
Sean gets a gold star for being helpful.
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