Field-Programmable Gate Arrays

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Quartus and simulation libraries...

Hi all, I used to work with Xilinx ISE, there you could compile the unisim, simprim libraries. I have switched from Xil...
1 comments posted 18yrs
posted by dontreplytothisaddy
1 comments posted 18yrs posted by dontreplytothisaddy

Xilinx EDK PPC405+FSL

hi i'm using edk 9.1 and i have to write my own ip core. i want to use the ppc405 in a virtex 4 an was wondering if tha...
1 comments posted 18yrs
posted by u_stadler
1 comments posted 18yrs posted by u_stadler

Emacs as GUI for NIOS-II

Which makefile should I use and where should the current working directory be located if I want to run a NIOS-II softwa...
0 comments posted 18yrs
posted by newsmailcomp6
0 comments posted 18yrs posted by newsmailcomp6

Xilinx's ML505

Hello group, Anybody know if DAC plugin modules exist for the Xilinx ML505/ML506 board ? Thanks, John
0 comments posted 18yrs
posted by John
0 comments posted 18yrs posted by John

FPGA program cable suggestion

Has any a good suggestion for a fpga program cable, which is known to work with linux (64 bits)? Thanks T.
1 comments posted 18yrs
posted by tralalal
1 comments posted 18yrs posted by tralalal

BGA reflow soldering using vapor phase

I am doing some initial research regarding PCB design process with a Spartan3E (FT256) .. Have i understood it correctl...
4 comments posted 18yrs
posted by kislo02
4 comments posted 18yrs posted by kislo02

Altera USB-Blaster on RHEL 5?

Has anyone worked out a hack to get the USB-Blaster to work with Red Hat 5? I need to put DE1 project boards in a lab w...
0 comments posted 18yrs
posted by ke9lc
0 comments posted 18yrs posted by ke9lc

Virtex BRAM Configuration

Hi Folks, I am totally new to FPGA design, so excuse me if this doesn't make sense. Is it possible to configure the 18K...
2 comments posted 18yrs
posted by sun.radha
2 comments posted 18yrs posted by sun.radha

MGT Transciever

Hi alll, I am trying to setup simple TX and RX communication using the MGT Transceiver without any 8b/10b encoding. I s...
2 comments posted 18yrs
posted by shakith.fernando
2 comments posted 18yrs posted by shakith.fernando

VCCIO issue on Xilinx Spartan3E !

Hi All, We are on a new board with on-board XC3S250E-VQ100. All VCCint are 1.2V All VCCaux are 2.5V Bank0 VCCio are 3.3...
5 comments posted 18yrs
posted by laurent.gauch
5 comments posted 18yrs posted by laurent.gauch

Darnaw module

Hi, I'm planning to purchase the Darnaw1 PGA module (http://www.enterpoint.co.uk/moelbryn/darnaw1.html). for my audio c...
3 comments posted 18yrs
posted by aramosfet
3 comments posted 18yrs posted by aramosfet

Xilinx Evaluation boad ISE sample project

Hello ! Does someone have verilog-HDL sample apply to Xilinx Evaluation boad [TB-4V-FX60-PRO] ? I want to sample source....
0 comments posted 18yrs
posted by life.is.dreaming
0 comments posted 18yrs posted by life.is.dreaming

Xilinx DCM outputs for DDR

Greetings, What's the best way to clock DDR flops from a DCM? In all the DDR I/O I've produced, I've always used the DC...
11 comments posted 18yrs
posted by newsgroup
11 comments posted 18yrs posted by newsgroup