Hi,
Has anyone used the ddr_sdr core
This core only uses the DQS lines for writing to the memory, and sets them as outputs. Therefore, during reads, both the FPGA and the DDRAM chip will drive them at the same time. Won't it be a problem ? Maybe not, thanks to the series termination resistors...but can anyone confirm ?
Regards,
Sebastien
Try looking to see how the output is set to a high impedance state during those read cycles.
KJ
Yes, that would be a problem. The FPGA shouldn't drive the DQS lines when the DRAM is driving them.
I can't imagine there is such an error in the design especially since its a crippled version of a commercial product (if memory serves me well). How are you sure the DQS lines are set as outputs the whole time?
Well, I thought that "out" signals in VHDL could not be set to high- impedance state, only "inout" signals could ; and that contention might not be a big problem with SSTL signaling, but I was wrong. After reading your replies I looked more closely at the code, and it sets the DQS outputs to 'Z' when reading. I did not think that could be possible.
Thanks,
Sebastien
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