I'm not very experienced at SMT PCB layout, but I'm trying to design a four-layer board with an XC3S50A-4TQG144. I'm using inner layers for
3.3V (Vcco, Vccaux) and GND. Am I asking for trouble if I route Vccint on the power plane? If I do that, should I just run traces between the four Vccint pins, cutting a "+" shaped region in the power plane, or should I give Vccint a square occupying most of the area under the package?
That works. Cut a square in the power plane, under the chip, and insert a smaller square of Vccint, so you can bring two supplies into the chip on each layer. Then you can route a fat trace in to power the inner island, with a few bypass caps, maybe on the backside of the board.
I would agree on the ground layer always because it is common to all power rails. We do have a product on 4 layers that has 7 power segments(4 Vccio, 1.2V, 2.5V and 3.3V) under the FPGA and so far with many hundreds of them in the field with many different customers no reports of power related issues. I will say we did a lot of work to make all of the power segments as good as we could using a number of techniques that we use frequently. The product in question is here
On this product we targetted 4 layers because we wanted to make a price target and 6 layers does cost more if only by a few dollars or the equivalent. If you are doing small numbers then PCB tooling may be of significance and that will be dearer on 6 layers than 4 layers. Standard lead times will also be greater on 6 layers than 4 usually
1-2 days and fast turn will cost more for a given target turn time.
Use sot23 style linear regs for 1v2 and 2v5 (for the 3e) and place them on the underside, within the FPGA. Then use the two signal layers to pour 1v2 and 2v5 to the fpga. The only limitation (for the 3e) is that all signals have to exit outwards from the FPGA.
I just assembled a 4-layer board with a EP2C8 (Cyclone II) in QFP. The stackup is sig/gnd/3.3/sig. The 1.2V core regulator is derived from the 3.3V and is near one corner of the FPGA. A very fat trace on the component side runs under the chip at the corner and forms a "Y" shape close to the inside perimeter of the pads. The Vccint is a little asymmetrical so that still leaves another corner open if you need it. I made the 1.2V PLL voltages (at the entry corner and the opposite corner) with cap+bead+cap. There's actually lots of room on the bottom, it's just a bunch of caps under the chip.
Like others have said, it's best not to mess with the ground plane. I have a four-layer S3E VQ100 board (1.2/2.5/3.3) that's somewhat ugly inside, but it works. Just divvy the power plane as best you can and run fat traces to the other pins.