Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Craignell FPGA DIP Module

Craignell user manual is now available http://www.enterpoint.co.uk/component_replacements/CraignellUserManualIssue1_00....
6 comments posted 18yrs
posted by g1
6 comments posted 18yrs posted by g1

Adaptive Best Practices

AJ Square's best practices consists of proven methods and processes that have developed to share with our customers and...
0 comments posted 18yrs
posted by rashida.guide
0 comments posted 18yrs posted by rashida.guide

problem simulating in modelsim - swiftpli_mti.dll

Hi There, I am getting the following error in modelsim when I try to simulate some thing. # Loading C:\Xilinx92i\smartm...
3 comments posted 18yrs
posted by sun.radha
3 comments posted 18yrs posted by sun.radha

Virtex-4 driving a 5V CMOS

Hi all, I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything wrong with simply using a pullup to...
5 comments posted 18yrs
posted by nospam
5 comments posted 18yrs posted by nospam

XST_BUFFER_TOO_SMALL

Hello, I am now using DeviceReadFrame function on Xilinx EDK9.1 sp2. But it returns "XST_BUFFER_TOO_SMALL". According t...
0 comments posted 18yrs
posted by hiroyuki.kawai0914
0 comments posted 18yrs posted by hiroyuki.kawai0914

Random Number Generation in VHDL

Hello members, I would like to know if VHDL already has functions defined to generate Random Numbers. If not, which wou...
28 comments posted 18yrs
posted by FPGA.unknown
28 comments posted 18yrs posted by FPGA.unknown

EDK 9.2i install issues in Linux

I know Xilinx does not officially support anything other than RedHat Enterprise Linux, yet so many people have installe...
3 comments posted 18yrs
posted by jaymode
3 comments posted 18yrs posted by jaymode

microblaze question

I'm investigating if the microblaze is an option for a project where physical space is extremely limited. Perhaps someb...
8 comments posted 18yrs
posted by tralalal
8 comments posted 18yrs posted by tralalal

Craignell FPGA DIL Module

Our Craignell webpage now has the schematics for the Issue2 40 pin version on it for all that have asked. Webpage is he...
0 comments posted 18yrs
posted by g1
0 comments posted 18yrs posted by g1

How to choose an FPGA for High speed applications

Hi all, I want to choose an FPGA for a High speed appliction so which one to go for either for Xilinx or Altera. But i...
3 comments posted 18yrs
posted by kiransr.ckm
3 comments posted 18yrs posted by kiransr.ckm

Type declarations

I am trying to use the following function defined in the ieee_proposed library -- to_signed (float) function to_signed...
2 comments posted 18yrs
posted by FPGA.unknown
2 comments posted 18yrs posted by FPGA.unknown

Pwm Sine Generation

Hallo to everyone, I should generate a pwm sinusoidal signal of a frequency lower than 500 Hz. I have seen DDS Compiler...
7 comments posted 18yrs
posted by marcotoschi
7 comments posted 18yrs posted by marcotoschi

data capture

Any (specific) advice on a simlpe and cheap Xilinx board for data capture? I want to capture about 5-10 minutes of digi...
1 comments posted 18yrs
posted by gil
1 comments posted 18yrs posted by gil