Field-Programmable Gate Arrays

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new to NIOS II

Hello group, Recently I have started to learn NIOS. I will appreciate it if somebody knows any good online resource or b...
2 comments posted 18yrs
posted by amit.kohan
2 comments posted 18yrs posted by amit.kohan

About 10-bit pixel datum from CMOS image sensor

Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am using a Spartan...
6 comments posted 18yrs
posted by tklau
6 comments posted 18yrs posted by tklau

Xilinx prom programming problem

I have a custom board with a V4 LX60 and a XCF32P config prom. I can config the FPGA directly via JTAG, but I cannot pr...
2 comments posted 18yrs
posted by sam
2 comments posted 18yrs posted by sam

PC requirements for ISE webpack

I am thinking of buying (or upgrading) my PC for an FPGA project. At the moment I am using a windows laptop for synthes...
10 comments posted 18yrs
posted by andy
10 comments posted 18yrs posted by andy

ROM/LUT

I'm trying to understand the intricacies of implementing a ROM in an FPGA. I've searched around and come up with some u...
5 comments posted 18yrs
posted by kmaryan
5 comments posted 18yrs posted by kmaryan

EPC in Xilinx EDK 9.2

I use External Peripheral Controller to access various peripherals from my MicroBlaze/PPC based systems. To allow acces...
0 comments posted 18yrs
posted by invalid
0 comments posted 18yrs posted by invalid

Regarding Hyperterminal

Hi, I have a quick question, and its been bothering me for at least 3 hours. So I made a project in EDK, and I simply w...
0 comments posted 18yrs
posted by clinileen
0 comments posted 18yrs posted by clinileen

question on record types

I have defined two functions as below function complexMult (a_i,a_q,b_i,b_q: signed) return complex is variable a,b : c...
1 comments posted 18yrs
posted by FPGA.unknown
1 comments posted 18yrs posted by FPGA.unknown

Xilinx PAR problem when using chipscope

Hi I have design that will PAR fine when chipscope is not included but whe it is I get the following error :- The place...
2 comments posted 18yrs
posted by maxascent
2 comments posted 18yrs posted by maxascent

define a new bust interface

hi all I want to work with xillinx edk and add an ethernet core to my design. I used hard-temac core and to connect thi...
2 comments posted 18yrs
posted by fmansoori
2 comments posted 18yrs posted by fmansoori

BPSK CORDIC tracking

Hi all, I would like to know how we can demodulate a BPSK signal with CORDIC algorithm. How can we (with CORDIC) make t...
1 comments posted 18yrs
posted by fpgaasicdesigner
1 comments posted 18yrs posted by fpgaasicdesigner

Spartan3 I/O question

I have a Spartan3 Bank VCCO pins connected to 1.8V. Normally I use this bank to generate 1.8V push-pull signals but I n...
3 comments posted 18yrs
posted by cpandya
3 comments posted 18yrs posted by cpandya

HDLC

Can anyone point me to a sight with HDLC schematic or drawings? Thanks
1 comments posted 18yrs
posted by romans5_8
1 comments posted 18yrs posted by romans5_8