Field-Programmable Gate Arrays

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Interface on board ADC to Spartan 3E startkit

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I...
15 comments posted 18yrs
posted by krunal.coep
15 comments posted 18yrs posted by krunal.coep

Antti needs a job

Our friend Antti is out of a job. Is there somebody in the Munich area who can offer a job, or some consulting ? I need...
9 comments posted 18yrs
posted by alfke
9 comments posted 18yrs posted by alfke

Embedded in Nurnberg

Hi c.a.f. folks for anyone wishing to say hello at Embedded, I am planning to be there on 28th afternoon, say will be a...
0 comments posted 18yrs
posted by Antti.Lukats
0 comments posted 18yrs posted by Antti.Lukats

Over utilization of FPGA resources

Hi, I'm currently facing a problem downloading my design to FPGA as my design has overutilized the FPGA resources (slic...
3 comments posted 18yrs
posted by veriqiang
3 comments posted 18yrs posted by veriqiang

Synthesis-Place-Route benchmark for i386-32bit

This is a benchmark test cd, to get performance data for a specific computer setup. Please contribute by posting a foll...
2 comments posted 18yrs
posted by fcdup8k
2 comments posted 18yrs posted by fcdup8k

Linux and the Digilent Basys ?

I work for a Linux software house and would like to offer a "Hello, World!" tutorial for FPGAs. The idea is to keep it...
4 comments posted 18yrs
posted by usenet
4 comments posted 18yrs posted by usenet

Ballpark PLB frequency

Hi, I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am somewhat conerned at the capabilities of the PLB b...
17 comments posted 18yrs
posted by stephenry
17 comments posted 18yrs posted by stephenry

distorted sine wave

I have written a process to generate sine wave. I am getting a distorted wave and not a pure sine wave. I am not sure i...
6 comments posted 18yrs
posted by FPGA.unknown
6 comments posted 18yrs posted by FPGA.unknown

Virtex 4 package layout

Hi I am laying out a board for a Virtex 4 FX20 in a FF672 package. Now woul it be ok if I connected some of the NC pins...
12 comments posted 18yrs
posted by maxascent
12 comments posted 18yrs posted by maxascent

Spartan 3 configuration download error

Hi, I am using the Xilinx ISEWebPack 8.1i together with a Spartan 3 Starter Kit (Digilent, bought from Xilinx). Now, fr...
7 comments posted 18yrs
posted by jboehm
7 comments posted 18yrs posted by jboehm