Field-Programmable Gate Arrays

Quartus 7.2sp2 memory exhaustion

Hi. I have Quartus 7.2sp2, MS Vista , and I have a project where I define ROM memory (with size 4096*32 bits). I define...

0 comments posted 18yrs

posted by drop669

0 comments posted 18yrs posted by drop669

HELP > Face/Edge detection on FPGA

Hi all I want to implement face detection on fpga Is there any free code available Or is there any code for edge detecti...

3 comments posted 18yrs

posted by sameemshabbir

3 comments posted 18yrs posted by sameemshabbir

Need info on systolic arrays in actual use

I need some references of where systolic arrays have actually been used in equipment or instruments. Thanks in advance,...

7 comments posted 18yrs

posted by Marco

7 comments posted 18yrs posted by Marco

real to signed

How to convert real to signed. The range of real will be from -1 to 1, -5 to 5, -10 to 10 and so on. I would like to co...

9 comments posted 18yrs

posted by FPGA.unknown

9 comments posted 18yrs posted by FPGA.unknown

DSP Ip Core

Hello all, I am looking for a free DSP Ip core (like the OpenCores C54). Have you some idea to look for ? Best regards,...

1 comments posted 18yrs

posted by jean.sebastien.leroy

1 comments posted 18yrs posted by jean.sebastien.leroy

Is there any way to disable JTAG for Sptantan3AN

Hi, We want to make Spartan3AN as One Time Programmable. We want to program it once and then disable JTAG. Is it possibl...

10 comments posted 18yrs

posted by togoli

10 comments posted 18yrs posted by togoli

What demokit and VHDL compiler pair to buy

I got Xilinx free IDE running and even got some simple designs through. But there wasn't any Xilinx programmer/evaluati...

2 comments posted 18yrs

posted by sala.nimi

2 comments posted 18yrs posted by sala.nimi

Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of...

18 comments posted 18yrs

posted by vladimir.v.korostelev

18 comments posted 18yrs posted by vladimir.v.korostelev

DCM Simulation : Input Clock Cycle Jitter

Hi Group, Just wondering if anyone has seen this issue. I am simulating a Xilinx FPGA design (RTL) containging DCMs. I...

2 comments posted 18yrs

posted by moogyd

2 comments posted 18yrs posted by moogyd

DSP newbie

I have written a process to generate sin wave as below. -- sine wave constants amp_sin : real := 10.0; phase_sin : real...

8 comments posted 18yrs

posted by FPGA.unknown

8 comments posted 18yrs posted by FPGA.unknown

Making changes to custom IP in EDK

I'm using EDK 9.1i. I have created custom IP using "Create or Import Peripheral", modified the VHDL files, and then imp...

8 comments posted 18yrs

posted by etorkild

8 comments posted 18yrs posted by etorkild

sd card slave interface

Now I want to design a SD card,for special use,I must use fpga to implement the interface between host controller and N...

4 comments posted 18yrs

posted by bjzhangwn

4 comments posted 18yrs posted by bjzhangwn

Using dma_sg_v2_01_a component with plb_ipif

Hi, I would like to interface a custom DMA controller to the user_logic created by "Create or Import Peripheral" in EDK...

0 comments posted 18yrs

posted by rajeevph

0 comments posted 18yrs posted by rajeevph

Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1

Hello all, I am writing to one of the software programmable registers (slv_reg0,1,2..) on a OPB slaves in the system us...

1 comments posted 18yrs

posted by narashimanc

1 comments posted 18yrs posted by narashimanc

Quicksim/modelsim

I am writing a testbench and one of the clock is a "gated clock" - meaning clock is clocking every time gate goes activ...

1 comments posted 18yrs

posted by martstev

1 comments posted 18yrs posted by martstev