Field-Programmable Gate Arrays

[Altera] How to infer some code into ROM-blocks (in automatic way), but not all

Hi. My qustion is probably dumb. But i'm stuck here. In my design I have a lot of code that can be inferred into ROM au...

2 comments posted 18yrs

posted by drop669

2 comments posted 18yrs posted by drop669

FPGA for a DVB common interface implementation

Hi, anybody has any (practical) information about the Common Interface specification for DVB receivers? I have some ide...

2 comments posted 18yrs

posted by manuel-lozano

2 comments posted 18yrs posted by manuel-lozano

PARAMETER C_SPLIT error

Hi, I'm working with the EDK 9.2 MicroBlaze Tutorial and get the following error message: ERROR:MDT - D:\work\xilinx\HW...

3 comments posted 18yrs

posted by is.er

3 comments posted 18yrs posted by is.er

reconfiguration of virtex 2 pro

Hi friends Can u please help me in reconfiguring virtex 2 pro board... Pls give an example and steps to reconfigure vir...

0 comments posted 18yrs

posted by maniraja84

0 comments posted 18yrs posted by maniraja84

verifying UNIFORM using matlab

I have written a process to generate random numbers using UNIFORM. I was trying to check the results using "rand" in ma...

7 comments posted 18yrs

posted by FPGA.unknown

7 comments posted 18yrs posted by FPGA.unknown

"Use Multi-level Logic Optimization" -- Advanced Fitting option

At the beginning of February, DJ Delorie proudly posted a bin2seven project. Since my entire reason to purchase a Spart...

2 comments posted 18yrs

posted by ddilbeck

2 comments posted 18yrs posted by ddilbeck

my Spartan-4 wishlist

here it is: 1) devices densities like in Spartan-3 (50..5000) 2) devices packages like Spartan-3E (including QN132 !) o...

21 comments posted 18yrs

posted by Antti.Lukats

21 comments posted 18yrs posted by Antti.Lukats

ICAP for readback on Microblaze...

Hi everybody, I'm trying to partially reconfigure my device (XC2VP30 on ML310 board) through ICAP. I have my ICAP attac...

1 comments posted 18yrs

posted by amirhossein.gholamipour

1 comments posted 18yrs posted by amirhossein.gholamipour

clock distribution accross boards

Hi, maybe you folks can help me with a design decision: I need to distribute a clock to up to ten identical boards. The...

13 comments posted 18yrs

posted by ksulimma

13 comments posted 18yrs posted by ksulimma

Virtex-5 FXT coming soon?

Hi, the fact that forum posting about ML507 was removed by Xilinx moderator (from Xiliinx forums), gives us at least th...

10 comments posted 18yrs

posted by Antti.Lukats

10 comments posted 18yrs posted by Antti.Lukats

FPGA/CPLD group on LinkedIn

FPGA/CPLD group on LinkedIn http://www.linkedin.com/e/gis/56713/3CC3BF77FD22 Group for People Involved In the Design an...

8 comments posted 18yrs

posted by wmwmurray

8 comments posted 18yrs posted by wmwmurray

Synplify crashing

I am using the Lattice ispLever tool for their PLDs and I seem to be having trouble with Synplify. It crashes frequentl...

1 comments posted 18yrs

posted by gnuarm

1 comments posted 18yrs posted by gnuarm

clock generation

hi i have a basic doubt in fpga implementation. i am new to this. i have made a stepper motor controller and implenting...

1 comments posted 18yrs

posted by srimankk

1 comments posted 18yrs posted by srimankk

Avnet/Memec V4FX12LC proto card and SysGen

Hi, Has anyone used this card with Xilinx System Generator to do hardware in the loop simulation. I can not find a boar...

2 comments posted 18yrs

posted by cwoodring

2 comments posted 18yrs posted by cwoodring

FPGA's be afraid, very afraid, of my wife!

Hi recent events: 1) trying to use Xilinx Cable III (actually Amontec chameleon) to program actel PA3 on protoboard usi...

5 comments posted 18yrs

posted by Antti.Lukats

5 comments posted 18yrs posted by Antti.Lukats