At the beginning of February, DJ Delorie proudly posted a bin2seven project.
Since my entire reason to purchase a Spartan 3e development board was to experiment, I decided to take DJ Delorie's project and experiment on how coding style and language effected XST/ISE final result. I stuck with DJ Delorie's original target of xc9572. The results were interesting, I will posted them on a website to be viewed later. But I did hit one giant stumbling block. "Use Multi-level Logic Optimization"!!!!
This option is on by default when you start a new project. The hurdle I hit is when this option is on, I fail to find a solution that maps to the target device. Instead of minimizing the design it actually causes the design size to be increased. The variant that first hit this issue uses 52/72 macrocells 181/360 Pterms,
8/72 registers
34/34 pins and 72/144 function blocks when this option is off. Which is less resources than all of the other variants of the original DJ Delorie design with the same options.
Has anyone else seen "Use Multi-level Logic Optimization" cause a logic explosion, rather than minimization? I am using ISE 9.2i, and XST for the synthesis. I have it set to minimize "Density". This is a tiny design. My concern is in the future when I am working on something more substantial, if I will always need to make sure this switch is disabled to ensure fitting in my target device.