I need help! Connecting my dual port RAM to a microblaze

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Hi there,
i have some problems while integrating a special dual port RAM core
(generated in xillinx ISE) into a Xillinx EDK project.

The ports of my DP-RAM are designed differently inorder to increase
the rate of data exchange. The DP-RAM size is 1Kbytes. The access on
the port A is byte-wise, so the resulting address length is 10 bits
wide. On the port B the access is 4-byte-wise, so that the resulting
address length is 8bits wide.

Inorder to connect this dual port RAM to a microblaze, I used an
ip_bram_controller which is a ready-made IP core in EDK.The
ip_bram_controller serves as the interface between the microblaze and
dual port RAM.
This ip_bram_controller has an address length of 32bit on both sides.

The signals of port A of my dual prot RAM are defined as external
signals and assigned to pins on an external board(FPGA board). The
signals of port B are then assigned to the signals of the
corresponding port on the ip_bram_controller.

This implies that the 8bit address bus of my dual port is assigned to
the 32bit address bus of the ip_bram_controller.All this is done
manually in EDK.

Here is the problem:
Inorder to generate a netlist for the components and consequent
bitstream for the design there is this persistent error which says the
address buses of 8bit and 32bit are not compartible.

My question is, how can i connect my DP-RAM directly to the opb bus,
without using a ip_bram_controller?

I have this error when i use the bram controller: G:\Fohtung
line 318 - 32 bit-width connector does not match 8 bit-width port

How can I get these two to match?

I'll be grateful for an answer. Thanks in advance!


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