Using TimeQuest Timing Analyzer


I'm trying to identify the critical path of a sequential circuit using the TimeQuest Timing Analyzer. However, I'm facing some dificulties because the tool doesn't provide, as the Classic Timing Analyzer used to do, any table showing the worst-case paths of the circuit. Instead, the TimeQuest generates a table with the Required Width, the Actual Width and the Slack refering to the pulse. How can I find, based on this provided information, the critical delay of the circuit?

Thanks a lot. Guirico C.

Reply to
Guirico C.
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You can tell Quartus to use the Classic Timing Analyzer by going into the Timing Analysis Settings.

Guirico C. wrote:

Reply to

Hi, Rob.

Thanks for answering. Actually, I can't use the Classic Timing Analyzer. I need to use the data obtained from TimeQuest, which is recommended by Altera for CMOS

65nm projects.

Guilherme C.

Reply to
Guilherme Corrêa

Hi, everyone.

Do you think that the best way of doing this is to compute the clock period based on the Fmax information? I know that it's not exactly the same of finding the critical delay of my circuit, but I can't think of another way. What do you think of it?

Guilherme Corr=EAa.

Reply to
Guilherme Corrêa

Hi Guirico,

The TimeQuest timing analyzer reports only a summary of the timing results by default during a full compilation. This is the worst-case slacks per clock domain in the reports ending in "Setup Summary", "Hold Summary", etc. found in the .sta.rpt file or in the messages.

You can also enable the option "Report worst-case paths during compilation" in the timing analysis settings to see the worst-case path per clock domain by default. To see more paths, open the TimeQuest timing analyzer GUI and use "Report Timing" to report more paths. There are many other options available as well.

For more information on the TimeQuest timing analyzer, please visit

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Hope this helps, Subroto Datta Altera Corp.

Reply to
Subroto Datta

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