I think someone here mentioned the possibility to configure an Xilinx Spartan-3E fpga with an SD-Card (MMC) in SPI mode. However when checking on this by chance today I found that it seems to not work because:
Read commands are defined as:
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READ_SINGLE_BLOCK 0x51 READ_MULTI.. 0x52
But Spartan-3E SPI uses the commands:
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Page79 Fast read 0x0B Read 0x03 Read array 0xE8
Or did I miss something?
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A
Antti
as:
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commands:
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Page79
think you missed something.
FPGA's can get configured from DATAFLASH mounted in SDCARD plastic (atmel sells those!) and sure mmc-sd can be used in spi or sd mode, but there is extra circuitry required, either mcu or cpld
Antti
S
sky465nm
I think my point was to accomplish this without adding an extra chip.. Using a MCU/CPLD it would ofcourse work.
A
Antti
well dont think it can be done, would be too good to be true ;)
Antti
J
job
as:
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Page79
SPI bus means to have one Master and one Slave.
SD card cannot be master, you need to have a Master to get the data from! FPGA CONFIG RAM cannot be master, you need to have a master to write the data to the FPGA RAM !
For programming FPGA, you need a master getting the data from SD and writing to FPGA RAM.
Larry,
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A
Antti
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SD card doesnt need to be master, the issue is that it is not compatible to the FPGA command used in master serial mode, etc.
with MMC card (not SD!) a RECONFIGURATION from MMC card could be possible, if
1 S3E is configured from SPI flash
2 S3E puts SPI flash into DEEP powerdown or any other mode that prevents configuration in case of PROG toggle
3 S3E prepares MMC card to enter STREAMING READ (not available on SD cards) mode and pre shifts instruction and address
4 S3E pulses its own PROG pin
5 S3E would be configured from a file located on the MMC card
so while INITIAL load from card is no way possible a repeated secondary configuration can be possible
S3E should be connected properly SPI flash and MMC card pins in parallel, MMC card should be operating in non SPI mode
Antti
J
job
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Do you mean a SD Card could be Master ?????
- Larry
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A
Antti
on
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no no, but when FPGA is configured as MASTER SERIAL then FPGA would generate CCLK if CCLK -> SD_CLK
and MMC preinited for streaming read then FPGA would clock out its bitstream from MMC card
Antti
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