case statements- verilog to vhdl

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I'm not a Verilog person, but I do have a book that shows both VHDL and Verilog code ("HDL Chip Design", by Douglas J. Smiths). The book shows that "//" is a Verilog comment. So, "// set default values" is a comment. The Verilog "default" is the same as the VHDL "when others =>". "always@ .. end" is the same as a VHDL "process .. end process". In your case (no pun intended), it's a combinatorial process. HTH

-Dave Pollum

The presence of "if reset" could imply that this is a clocked process, not combinatorial. We can't tell because the "always" statement is not included, and we cannot tell if the block is also sensitive to posedge clock.

Andy

//

I have 2 case statement in 1 always loop in my verilog file. I am not sure how this should be implemented in VHDL. I am aware of the syntax. =46rom design point of view I am not sure if I should be putting them in

2 seperate process statements.

Verilog =3D>

always @ posedge clk c1 : case(cmd) is when a =3D> bunch of statements when b =3D> bunch of statements when c =3D> bunch of statements when d =3D> bunch of statements default =3D> bunch of statements end case c1

c2 : case(cmd) is when a =3D> bunch of statements when b =3D> bunch of statements when c =3D> bunch of statements when d =3D> bunch of statements default =3D> bunch of statements end case c2

end

My question is

1) Is the VHDL equivalent of the above, 2 case statements in one process or 2 different processes with 1 case each? The problem with 2 processes I am facing is access of varaibles. 2) The above is similar to an FSM. One case statement is executing the present command, while the other is completing the last command. Any idea on how this should be converted to VHDL?

No. One verilog block is one vhdl process.

one process

Did the verilog version work?

-- Mike Treseler

The verilog code works but I havent deisnged it. So, I am not sure how its implementation in VHDL woould be.

Unless you post the code, neither am I.

-- Mike Treseler