Field-Programmable Gate Arrays

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DDR2 termination

Hi, After reading over the documentation for DDR2 and the SSTL signalling standard, I have a question about the role of...
1 comments posted 18yrs
posted by stephenry
1 comments posted 18yrs posted by stephenry

beginner

Xilinx Spartan 3E starter kit. process (boff, bon ) begin if (boff= '1') then led
1 comments posted 18yrs
posted by meralonurlu
1 comments posted 18yrs posted by meralonurlu

altera technical question?

hi all: I have a question about stratix II .An oscillator must drive a constant clock frequency to an FPGA pin. The max...
2 comments posted 18yrs
posted by andy730215
2 comments posted 18yrs posted by andy730215

FPGA JTAG commands

Hi, I am trying to access a QuickLogic FPGA via JTAG. I am using a FTDI DLP2232M-G (and associated FTCJTAG api) to conn...
1 comments posted 18yrs
posted by tom_kuhn
1 comments posted 18yrs posted by tom_kuhn

DMA_BURST_SIZE in Xilinx EDK 9.1i

Hi, i have generated a user ip with dma/sg support. now i want to disable the dma burst transfer. -- specify the size (...
0 comments posted 18yrs
posted by fatfpga
0 comments posted 18yrs posted by fatfpga

VHDL refactoring tools

Greetings All, I've just spent 20 mins editing 12 VHDL files to add two signals and route them up and down a design hie...
1 comments posted 18yrs
posted by christopher.saunter
1 comments posted 18yrs posted by christopher.saunter

Error while doing 'Generate Netlist' in xilinx 9.2i

Hi all, When I do Generate Netlist in Xilinx 9.2i, I get the following error - ------------------------- ./synthesis.sh...
2 comments posted 18yrs
posted by mehrotrasaransh
2 comments posted 18yrs posted by mehrotrasaransh

Synplify beeping

I am running Synplify from the Lattice ispLever tools and every time I compile the design Synplify beeps when it is sta...
7 comments posted 18yrs
posted by gnuarm
7 comments posted 18yrs posted by gnuarm

which commercial HDL-Simulator for FPGA?

As commodity PC hardware and prouctivity applications deline in price, EDA tools are as (relatively) expensive as ever,...
38 comments posted 18yrs
posted by fpgas
38 comments posted 18yrs posted by fpgas

NVIDIA’s Tesla T10P Blurs Some Lines

What do you guys think about that?: http://www.embeddedtechjournal.com/articles_2008/20080617_nvidia.htm I heard about...
18 comments posted 18yrs
posted by prdubois
18 comments posted 18yrs posted by prdubois

Question about coefficient padding

Hi, In the document of FIR Complier v3.2, it talks about coefficient padding. I have several questions about that topic...
0 comments posted 18yrs
posted by rxjwg98
0 comments posted 18yrs posted by rxjwg98

Stratix II GX EP2SGX90FF1508C3N

I also have 34 pieces of the Stratix II GX, the part number is EP2SGX90FF1508C3N Best Regards, Jon E. Hansen (949)864-77...
0 comments posted 18yrs
posted by jon
0 comments posted 18yrs posted by jon

Mapping the DCM clock output onto a global buffer

Hello, I am using a Xilinx Spartan-3 FPGA (XC3S200-4), and I am having difficulty mapping the Digital Clock Manager (DC...
7 comments posted 18yrs
posted by ghourihan
7 comments posted 18yrs posted by ghourihan

MIG core generator problem

Hi, I have one question about Memory Interface Generator. This problem I can't solve for a period of time so I decided...
1 comments posted 18yrs
posted by Zorjak
1 comments posted 18yrs posted by Zorjak