Translate problem

Perhaps you forgot to include the libraries?

library unisim; use unisim.vcomponents.all;

HTH

-P@

tance

even after including in my top.vhd also cannot. Im still getting the same error But when i remove...

INST DCM_SP_INST CLK_FEEDBACK =3D 1X; INST DCM_SP_INST CLKDV_DIVIDE =3D 2.0; INST DCM_SP_INST CLKFX_DIVIDE =3D 1; INST DCM_SP_INST CLKFX_MULTIPLY =3D 2; INST DCM_SP_INST CLKIN_DIVIDE_BY_2 =3D FALSE; INST DCM_SP_INST CLKIN_PERIOD =3D 20.000; INST DCM_SP_INST CLKOUT_PHASE_SHIFT =3D NONE; INST DCM_SP_INST DESKEW_ADJUST =3D SYSTEM_SYNCHRONOUS; INST DCM_SP_INST DFS_FREQUENCY_MODE =3D LOW; INST DCM_SP_INST DLL_FREQUENCY_MODE =3D LOW; INST DCM_SP_INST DUTY_CYCLE_CORRECTION =3D TRUE; INST DCM_SP_INST FACTORY_JF =3D C080; INST DCM_SP_INST PHASE_SHIFT =3D 0; INST DCM_SP_INST STARTUP_WAIT =3D FALSE;

from my constraints file...i can do it w/o any error.

should I remove them?

Since the instance is inside another module, you have to specify the complete path to the instance you want to constrain, e.g.

INST clockmanager_inst/DCM_SP_INST CLK_FEEDBACK = 1X;

... and so on. clockmanager_inst is the instance name for the clockmanager-module you use in your top level.

You can use attributes in your VHDL-code instead of specifying constraints in the UCF, or you can specify GENERICs when instantiating. See

HTH, Sean

nstance

ONOUS;

thanks.. it solved the problem.

I've been trying out the following code with TEMPUART.VHD as my top module on my UART. I connected the Uart of my spartan to my PC using a null modem connection.

It's weird cause I never seem to be able to get the data I output , FF and 0A, on my PC. I get 7F instead of FF...

ct instance

de

NCHRONOUS;

RUE;

g.

i've set on the PC side to 8bits with no parity. but i can only get 7F instead of FF