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OpenCore.org DDR SDRAM problems

hey,

i needed a ddr sdram controller for a MT46V16M16 so when i saw the IPCORE on OpenCores.org i thought why not use it ... so i have build all the necessary controlling processes and blocks and simulated it and tried it out on a virtexII FPGA and worked fine, then i connected the DDR controller to it at i got this HUGE list of warnings about unconnected elements. (i attached it to this message for the curious one among you) and i was just wondering if other people already had this problem and maybe solved them... any help is welcome ...

thanx in advance,

kind regards,

yttrium

P.S. this is just on part of the project: in this part data has to come from a pc through uart towards RAM and the on VGA/PAL (all the necessary parts for this part have been done and tested, so only the ram controller fails to do his job ;-) ...)

P.P.S. just found out that this newsgroup will not accept attachements from me ;-)

INFO:Xst:1317 - HDL ADVISOR - A dynamic shift register was found for signal and currently occupies 2 logic cells (1 slices) for the flip-flop chain and additional logic cells for the multiplexer. Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. INFO:Xst:1317 - HDL ADVISOR - A dynamic shift register was found for signal and currently occupies 2 logic cells (1 slices) for the flip-flop chain and additional logic cells for the multiplexer. Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. INFO:Xst:1317 - HDL ADVISOR - A dynamic shift register was found for signal and currently occupies 2 logic cells (1 slices) for the flip-flop chain and additional logic cells for the multiplexer. Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. INFO:Xst:1317 - HDL ADVISOR - A dynamic shift register was found for signal and currently occupies 2 logic cells (1 slices) for the flip-flop chain and additional logic cells for the multiplexer. Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.

and

WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block .

and

WARNING:Xst:1710 - FF/Latch (without init value) is constant in block . WARNING:Xst:1710 - FF/Latch (without init value) is constant in block .

are some of the warnings i get from the controller

Reply to
Yttrium
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Hi Yttrium, I had managed to get that core up and working with ISE5, but have been having trouble since migrating to ISE6. I made some changes to my code at around the same time, though, so I'm 99.99% certain it's my problem... One thing I found was that I needed to increase the REFRESH_WINDOW constant in ddr_sdr_conf_pkg.vhd to 18 to avoid problems with some combinations of write-with-precharge commands interfering with the refreshing of the memory. This is a quick-and-dirty fix, with certain costs in terms of performance, but it makes things stable. See below for my comments on your warnings...

The first group of warnings are just some helpful suggestions by ISE telling you that the shift registers could be packed into SRL16 components instead of using a bunch of flip-flops if you can forego using reset pins.

If you look at the source code, you'll notice that shift_q is actually a

2-stage FIFO (data_in->shift_q(0)->shift_q(1)->ddr_data) used to delay input data. The lower bits of shift_q(1) aren't actually used, though (ddr_data

I'm guessing that the 2 LSb's of your address are never modified, i.e. you increment your address by multiples of 4?

So overall, the warnings you get seem fairly benign (although I can't really say for sure for the one about ddr_ram_module_row_adr_q). Warnings aren't necessarily bad. Check each one, and if you know that it's not a problem, ignore it, or change the code so that the warning doesn't appear (if possible).

--
Pierre-Olivier

P.S. Text is always better than attachments in newsgroups.  Cut down 
what you have to the bare essentials and then present it in text form. 
This avoids many problems for many people and increases the chances of 
people responding to your mail.

-- to email me directly, remove all _N0SP4M_ from my address --
Reply to
PO Laprise

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