Hi all! I am developing the firmware for a small project. I've completed the design prototype stage in a XC4036-3HQ240 and I have had no major problem. When I "passed" (re-synth and P&R for the new part) the design to the final device (XQ4036-3PG411) I've noticed that I'm unable to place a single FF/Latch to work (10MHz). The same code works as expected in the commercial version. The configuration process is performed through the JTAG chain and is OK (done high) as all combinational assignments are OK, but no sequential (FF/Latch), independent on location of FF/Latch or of Startup/BUFGP instantiation.
The symptoms resemble to reset being permentely asserted but I have the reset pin hardwired to GND and the code performs reset when reset=1. This implies that the chip is only reseted by the power-on-reset performed when loading the bitstream. It doesnt seem to be this.
I'm using Leonardo for synthesis and Webpack Classics (ISE 4.2.03i) for P&R and programming.
If any one as ever passed through this problem or have any idea how to solve it please let me know.
Tanks in advance, Rui Ferreira
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--This test code should generate a 5MHz clock on test_clock_o;
--output signal is always stuck at reset value ('1'); LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY newtest IS PORT ( comm_clock_i : IN STD_LOGIC; --10MHz signal comm_reset_i : IN STD_LOGIC; test_clock_o : OUT STD_LOGIC ); END newtest;
ARCHITECTURE rtl OF newtest IS
SIGNAL test_clock : STD_LOGIC;
-------------------------------------------------------------------------------- BEGIN
p_process : PROCESS (comm_reset_i,comm_clock_i) BEGIN IF (comm_reset_i='1') THEN
--reset test_clock