Xilinx version ROM with automatic increment

to

version

Hi

You could investigate if you can use the Xilinx utility "Data2BRAM". It changes the bitfile to manipulate data in the BRAMs.

/Pfna

You could try to locate the init value for this register in the bit file, and then use a PERL or whatever script to automatically increment it after each P&R iteration. I'm not familiar with the details of Xilinx bitstreams, but I guess you'll have to also update some kind of CRC after doing this.

Another suggestion would be the USERCODE register ; its value can be set with the bitgen -userid option, and read out via JTAG.

If you have an external PROM, you may have a look at XAPP694 (Reading User Data from Configuration PROMs).

Have fun, Guy.

H=E5k> Hi,

have to

version

.bit

Håkon -

I faced a similar problem recently (in a Verilog design).

I ended up writing a Perl script that puts the current time stamp in an include file. The next time the design synthesizes, it gets the new date. Note that it requires a re-synthesis, it will not increment on just a new routing.

If you're interested in this, look back through this news group for the article I posted. The thread was around July 21.

John P.

Thank you, I'll look into that. BR Håkon