Xilinx ISE WebPack Simulation Problem

I am trying to perform a simple behavioral simulation of a baud rate clock generation module. The module is straightforward and will synthesize properly, so I am fairly confident that it is written correctly. However, just to verify, I want to simulate it.

I create a test bench waveform file and set up the clock @ the correct frequency, set all of the inputs properly, and save the file.

When I run the simulation, I have the following problems:

1) All of the inputs which were set and saved now appear as high impedance 2) Additional output signals which were not present in the test becnch waveform now appear such as PERIOD[31:0] 3) All of my outputs of interest appear as X (unknown)

Any thoughts / suggestions?

Thanks, Scott

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That's a somewhat backwards approach. First you need to get the behaviour correct in simulation and THEN synthesize it. Correct behaviour in simulation is what gives you confidence that what you've written will implement whatever function it is that you want to do. Getting through synthesis simply says that what you've written (whether it is functionally correct or not) can be implemented.

Ultimately both are important, but most experienced designers concentrate on getting function correct (as verified by the simulator) and then (or as a background task while simulating) run through synthesis to make sure that when they really are ready to synthesize there won't be any surprises.

Sounds like one of the following:

- The 'inputs' are actually I/O pins

- Or this is a post route simulation and you're not actually forcing the inputs to anything and the post-route simulation model drives them to a high impedance state.

- Or, if this is a post route simulation than however it is you're forcing your inputs you're not overriding the 'Z' drive of the post route simulation. Check to see how you're forcing these inputs, look for something like a 'freeze' option, which says that the 'force' statements override anything else. Basically double check how it is you're providing stimulus to your design, it doesn't look like you're doing it correctly.

Sounds like you're not simulating the top level of your design then....presumably PERIOD[31:0] is some internal signal that is not supposed to be at the top level of the design....so figure out exactly what entity you're simulating.

Most likely because your inputs are not being forced correctly (see above).

Kevin Jennings

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