We have a Spartan6/45 that's talking to 16 separate SPI A/D converters. The data we get back is different, but the clock and chip select timings are the same. To get the timing right, avoiding routing delays, we need our outgoing stuff to be reclocked by i/o cell flipflops.
So what happens is that we have one state machine running all 16 SPI interfaces. We tell the software that we want the adc chip select flops in i/o cells. The compiler decides that all are seeing the same input signal, so reduces them to one flipflop. Then it concludes that that flipflop can't be in an i/o block, and builds it that way. The resulting routing delays are deadly.
We couldn't find a way to force these 16 flops into IOBs. Really.
The fix is to fool the compiler into thinking the flipflop states are not the same. Turns out the the synchronous clear inputs to the flops are unused in our design. My suggestion was to ground an input pin, run that into the serial input of a 16-bit shift register, and route the sr taps to the clears of the 16 output flops. The compiler can't know that these levels are in fact always low, so has to gen 16 different flops. *Then* it allows the flops to be forced into IOBs.
Rob has a better idea, just make a 16-bit SR that generates a thermometer code on powerup, namely walk a 1 into it, and have the sr output bits un-clear the i/o flops sequentially. The compiler isn't smart enough catch onto that, and we don't need to ground a pin.
Isn't that all perfectly stupid?
The Altera folks are coming to make their pitch tomorrow. This story may amuse them.