Xilinx Dual processor design

I think the biggest obstacle is lack of hardware cache coherency. There's a big Xilinx appnote on 2 PPC setups, though:

naresh schrieb:

That depends on your operating system. The PPC405 has no support for cache coherency so a system with physically shared memory can't use the caches out of the box. If you're only using the on-chip BRAMs this won't make much a difference. If you have to use external memory it will kill your performance.

Maybe there is a way to implement a mixed hardware/software support for cache coherency. Building a module to snoop the memory buses of the PPC405s shouldn't be much of a problem but you have to be sure that you see all memory transactions. Bad luck if the cache is write-back.

So all in all throwing Linux with a SMP kernel on it won't work.

Depending on your requirements you can run two instances of the xilkernel, one on each of the PPC405s. Those systems can communicate with a shared PLB-memory block and control access to other modules with the opb_mutex.

Best regards, Andreas

Hi,

I'm actually working in a port of xilkernel for SMP systems. It actually works with 2 to 8 MicroBlazes, but I haven't ported it to PPC yet. Performance is not as good as expected due to the impossibility of using data caches.

For using with PPC I think you can use eCos, that has support for PowerPC and SMP systems, but I have never used it.

Regards,

Pablo H