Hi,
I experience problems with some "normal" IO's(not dual purpose IO's) on a Xilinx Virtex2p50ff1517. I observe that these IO change value during configuration and after configuration these IO are not high impedance as intended, but either high or low. These IO's are part of a processor interface where the other IO on this bus is high impedance. I have checked in FPGA Editor and find that there the "strange" IO's are implemented exactly as the "normal" IO's (the same signal is driving the output buffer).
Do any of you have any suggestion to what have gone wrong. Is the chip damaged or is there something wrong with the configuration procedure. I tried both slave-serial and JTAG programming but the behaviour is the same.
John