I've a project with a powerpc and some userperipherals (connected through ipif at the plb bus). The plb bus is running at 100 MHz and the powerpc is running at 200 MHz. In a virtex2pro vp30 device (speed grade5) this design is giving no problems with building (all timing constraints are met).
Now I changed the design to use it in a virtex4fx60 (speed grade 10). The plb bus frequency is increased to 125 MHz and the powerpc to 250 MHz. Now I get timing errors. Is this unexpected? (I mean it's only an increase of 25 percent, but the used device is a virtex 4; I was expecting that this small frequency change shouldn't give any problems for a virtex 4).
Does anyone have experience with running the plb bus at 125 MHz and using the ipif interface?