What does + synthesize to?

Hi all,

Lets assume I'm using a Xilinx Virtex device and I have a VHDL design that includes the following

a

Hi Kload!

With no synthesis costraints: carry-ribble-adder, because it's the smallest.

With speed-constraints: Depending on the synthesis tool and target library. Often Carry-Lookahead.

With something like "synthesis pragmas" (supported by Synopsys) you can manually choose the type of adder.

Ralf

Well, if you have the tools, why don't you have a look at the results? Just use the Floorplanner or the FPGA Editor.

If nothing helps, try a more recent version. You may wish to have a look at the xilinx home page.

BR Chris

Kload wrote: