I am interested in looking at the breakdown of resource utilization for a design I have done in a Virtex-II Pro (in ISE 8.2), broken down on based on the design hierarchy. I've seen in the past that you can do this using Floorplanner, however when I attempt to, I get the following message...
"Design contains macros with RPM grid coordinates which are not supported by Floorplanner."
I've looked into the error and based on the following Xilinx Answer [I realize it is 6.2 but I assume the essence still applies]
NOTE: These solutions will not work if any of the cores have hardware multipliers because the RPM_GRID system must be used with multipliers.
Does anybody know a way to either: a) use Floorplanner on my design, or b) get the information I am interested in from another Xilinx tool?
Thanks in advance for all your help!