Discrepancy in CLB Usage Report

Jul 02, 2003 1 Replies

Rate this thread:

Anand P Paralkar 23 years ago

Hi,

I am using the following flow:

VHDL - Entry Synplify Pro - Synthesis Xilinx Design Manager - Post synthesis, place and route, etc.

The target device is Xilinx Spartan XL - XCS20XL.

I am trying to understand the two summaries:

Synthesis Summary -------------------- Logic Mapping Summary: FMAPs: 243 of 392 (62%) HMAPs: 83 of 196 (43%) Total packed CLBs: 173 of 196 (89%)

Vote

Ken McElvain 23 years ago

Look into why you have so many (147) luts used as route-throughs.

3 input LUTs: 230 (147 used as route-throughs)

230 - 147 = 83 = HMAPS reported by Synplify Pro.

You can go into FPGA editor and see what the configuration is for some of these route throughs.

Anand P Paralkar wrote:

Vote

Join the Discussion

Have something to add? Share your thoughts — no account required.

Ask the community — no account required