DCM and Maximum Frequency implied by XST

In a design: case 1) using a clock (divided whith a "vhdl process" 25Mhz from 50Mhz) so that the remaining of the desing use the divided clock and a minor part use the original clock... ...then the XST report show:

Device utilization summary:

--------------------------- Selected Device : 3s200ft256-4 Number of Slices: 1798 out of 1920 93% Number of Slice Flip Flops: 630 out of 3840 16% Number of 4 input LUTs: 3500 out of 3840 91% Number used as logic: 3244 Number used as RAMs: 256 Number of IOs: 143 Number of bonded IOBs: 143 out of 173 82% IOB Flip Flops: 32 Number of BRAMs: 6 out of 12 50% Number of GCLKs: 2 out of 8 25%

Timing Summary:

--------------- Speed Grade: -4 Minimum period: 26.113ns (Maximum Frequency: 38.295MHz) Minimum input arrival time before clock: 13.848ns Maximum output required time after clock: 12.917ns Maximum combinational path delay: No path found

_._._._._._._._._._._._._._._._._._._._._._._._._._._._._._.

In the same desing but: case 2) using a dcm to syntetize a frequency (35Mhz from 50Mhz) so that the remaining of the design use the dcm output as clock and a minor part use the original clock... ...then the XST report show:

Device utilization summary:

--------------------------- Selected Device : 3s200ft256-4 Number of Slices: 1610 out of 1920 83% Number of Slice Flip Flops: 657 out of 3840 17% Number of 4 input LUTs: 3137 out of 3840 81% Number used as logic: 2881 Number used as RAMs: 256 Number of IOs: 143 Number of bonded IOBs: 143 out of 173 82% Number of BRAMs: 6 out of 12 50% Number of GCLKs: 1 out of 8 12% Number of DCMs: 1 out of 4 25%

Timing Summary:

--------------- Speed Grade: -4 Minimum period: 63.448ns (Maximum Frequency: 15.761MHz) Minimum input arrival time before clock: 14.704ns Maximum output required time after clock: 12.091ns Maximum combinational path delay: No path found

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Anyone knows if it can be a normal behaviour (I'm pointing in particular the Maximum Frequency 15.761MHz using the DCM vs

38.295MHz not using it)... ...or better ;-) I done some mistake somewhere?

thaks in advance Sandro

Reply to
Sandro
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Reply to
Peter Alfke

Peter, thanks a lot for the hint... Modifying some interrelations between the two clock domains and using DCM now I obtain:

Timing Summary:

--------------- Speed Grade: -4 Minimum period: 18.284ns (Maximum Frequency: 54.694MHz) Minimum input arrival time before clock: 14.734ns Maximum output required time after clock: 12.789ns Maximum combinational path delay: No path found

I'm not sure the changes I done are "semantically" wath I want but now I "know" that I can (?must?) improve something in the design.

Regards Sandro

Reply to
Sandro

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