Maximum frequency

Hi all,

Iam using Xilinx XST for synthesis. Iam using almost 20 modules in my design. each if i synthesize seperately iam getting a maximum frequency of more than 400 Mhz. But when i combine everything iam getting only 121Mhz.

Can you tell me the reason...??? Does this mean i cannot use a clock more than 121 Mhz in my design(iam using and found it working well..) How can i increase my timing for high frequencies..?? Iam providing the synthesis report here. Can you tell me what is the Maximum frequency mentioned here..?

Timing Summary:

--------------- Speed Grade: -1

Minimum period: 8.226ns (Maximum Frequency: 121.566MHz) Minimum input arrival time before clock: 3.043ns Maximum output required time after clock: 3.281ns Maximum combinational path delay: 2.072ns

I want to acheive minimum 400Mhz for my entire design.... Is it possible...? That is my target.... Do comment...

Reply to
Loading thread data ...

More modules means more overall space used in the chip, means longer lines from one to the other, means more delay.

You'll want to ask the guys over in comp.arch.fpga about that --- down the hall, next door on the left. For now, I'll just say that if you have to ask, you had better believe the answer the tools gave you.

Reply to
Hans-Bernhard Bröker

With this design, most probably not. 121MHz is _way_ short of 400. Depending on your particular design, there are methods of making it run faster... but you need to understand to some degree how the synthesiser realises your design before you can even start...


Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
 Click to see the full signature
Reply to
Mark McDougall

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.