Iam using Xilinx XST for synthesis. Iam using almost 20 modules in my design. each if i synthesize seperately iam getting a maximum frequency of more than 400 Mhz. But when i combine everything iam getting only 121Mhz.
Can you tell me the reason...??? Does this mean i cannot use a clock more than 121 Mhz in my design(iam using and found it working well..) How can i increase my timing for high frequencies..?? Iam providing the synthesis report here. Can you tell me what is the Maximum frequency mentioned here..?
--------------- Speed Grade: -1
Minimum period: 8.226ns (Maximum Frequency: 121.566MHz) Minimum input arrival time before clock: 3.043ns Maximum output required time after clock: 3.281ns Maximum combinational path delay: 2.072ns
I want to acheive minimum 400Mhz for my entire design.... Is it possible...? That is my target.... Do comment...