Hallo.
Where to find HDL-models of CLBs, so one could instantiate them directly (or just to get a basic idea of what's efficiently implementable)? The Xilinx datasheets aren't really clear about the CLB-structure, I think. For example, after having read then SpartanII datasheet, I still even don't know, how many signals go out of a CLB, and which functions can be programmed with a CLB.
Gruss
Jan Bruns
There are LUT models but not CLB models.
"General Schvantzkoph":
Hm, why? I've tried to create an LC-model, but I'm not sure, if it will synthesize correctly, if used within an slice/CLB-model:
Gruss
Jan Bruns
`include "c:\xilinx\verilog\src\ise\unisim_comp.v"
module spartanII_LC(gin1,gin2,gin3,gin4,carryin,directin,xorinL,xorinC, lutoutL,lutoutG,sumoutL,sumoutG,andoutL,carryoutL,carryoutG);
input gin1,gin2,gin3,gin4; output lutoutL , lutoutG; output andoutL ;
input carryin; output carryoutL,carryoutG; input directin; //may be andoutL (or "B"=directin ???)
input xorinL , xorinC; output sumoutL, sumoutG;
LUT4_D lut(.I0(gin1),.I1(gin2),.I2(gin3),.I3(gin4),.O(lutoutG),.LO(lutoutL)); // synthesis attribute INIT of lut is "abc7"
MULT_AND multand(.I0(gin1),.I1(gin2),.LO(andoutL)); MUXCY_D carrylogic(.S(lutout),.DI(directin),.CI(carryin), .O(carryoutG),.LO(carryoutL)); XORCY_D xorcarry(.LI(xorinL),.CI(xorinC),.O(sumoutG),.LO(sumout)); endmodule
The Spartan-II data sheet was a disappointment as far as the CLB graphics went, but... The Virtex (not Virtex-II) CLB structure is exactly the same as the Spartan-II and that data sheet *does* have beautiful detail. I've had a full-page print of the CLB graphic on my cubical wall for a few years now. The only thing I needed to add was the 0 and 1 input orientation to the F5, F6, and CY muxes.
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