Virtex 5 announced

ISTR that Altera define differing delay times, for their LUT inputs. Will Xilinx define to that level of detail now, as well ?

-jg

yes Altera uses different LUT delays for different inputs to achive better timing

Antti

Jon,

The 4VFX40 and FX140 were taped out, with first samples available 4th Q

I would suggest using the FX60 for development for a FX40 design.

Check with your FAE for status. But now that we have fixed things, these should go smoothly.

Sadly, the fixes to the MGTs did affect the timeliness of the rollout (an understatement if I have ever made one). Let us be honest; IT MADE US LATE! YES, L A T E.

And we are very sorry, and we promise not to ever make those mistakes again.

All the other parts (FX12, 20, 60, 100) are available as 'CES4'.

If anyone wants to berate us for their FX experience on V4, please do (we deserve it). All I can say is that we have finally fixed things, and are shipping, and will go to production now that we have that over and done with.

From the lash marks on the senior execs, I'd say our customers were very expressive with their displeasure, and a lot of processes and procedures got changed when it comes to announcing anything. Especially anything with analog content. We also have learned a lot about making gigabit transceivers that will work flawlessly, work identically, and yield well.

Austin

J> Aust>

Antti,

So do we.

Aust> "Jim Granville" schrieb im Newsbeitrag

Originally the V4FX series was supposed to support quad date rate (10GHz), is that ever going to happen or has Xilinx given up on that? In the InfiniBand world QDR is going to start happening in the 2007 time frame so it would be nice if QDR RocketIO were to become available next year in either the V4FX or V5FX.

Also do you plan to add hardware CRC16s to the V5FX? The V4FX had hardware CRC32s but not CRC16s, having both would be a big help.

One final thing which is a tools issue and has nothing to do with the hardware. Please provide separate models for the CRC32s, tying them to the RocketIO models is a major pain. The CRC32 may be physically located in the same tile as the SerDes but logically it's independent. It makes as little sense to combine the CRC32 model with the SerDes model as it would to tie the Block RAM and Multiplier together. Those components are also next to each other but you provide separate models. One final thing, please provide Verilog behavioral models for the RocketIO instead of those awful SMART models. SMART models slow down the simulation and their lack of transparency complicates the debug process.

Yes, thanks. I'll admit I took the 'Lower' in your sentence

" Lower dynamic power, and equivalent static power, today."

as applying to all clauses.

I do see the curves and infos, are rather sparse on revealing the _actual_ Static Icc numbers - as dynamic Icc keeps improving, the static Icc is going to become a larger % of the power budget....

-jg

So the luts are actually full multiplexers, not a memory array style of addressing? I would have thought LUTs would work much better than general multiplexors by using a nand/nand style of structure to drive one active line in a 64-wide CMOS tree. Muxes?

Jim, the short answer is yes, and even for Virtex-4. There is a limit to the numbers given in the data sheet, but Xilinx software has, for several years, documented (and has taken advantage of) the differences in LUT through delay from the various inputs. In the battle of picoseconds, these small delay differences become important

To Antti: The reason for only 32 bits in the SRL32, even though the LUT6 has 64 latches, is different: In previous generations with SRL16 in a LUT4, we used a circuit trick (capacitive storage) to avoid using a master latch plus a slave latch, which is the conventional way to build flip-flops or registers, even shift registers. For ever smaller transistor geometries, such "old-fashioned tricks" do not scale well, and we went back to a conventional register implementation, with two latches per flip-flop, thus only 32 shift register bits in a LUT6.

Thanks for the interest in Virtex-5. We are all very excited about our new and very healthy baby... Peter Alfke,

When will this topology be available in Spartan families ?

-jg

I can use google, too.

None of these links are actually referring to a real product, and most are referring to Xilinx (without naming us, like the Altera quote).

Austin

John_H schrieb:

In a RAM you can reuse the decoder logic over many bitlines. For a single bit output adress decoders are larger, slower and have higher capacitance compared to pass transistor muxes. Maybe there is a sweet spot a little off from the extreme so maybe the tree has one or two levels less and uses one input as enable (or wordline if you like). But I am sure that most of it is a tree of pass transistors.... After all the technology used is highly optimized for pass transistors.

Also: A MUX build with address decoders enabling a common bitline is still a MUX...

Kolja Sulimma

Hi Austin,

LX datasheets says up to 10 DSP48E colums per device, but the largest of the LX family, LX330 only has 2 not 10 DSP48E columns?

Are devices that actually have 10 columns already planned? Scary to think how larger would the be!

Antti

Hi Peter,

interesting, as much as I recall at the time Altera was claiming to support LUT input delay difference in their tools, Xilinx had no public info that the input delay are different or that they are actually calculated compensated in Xilinx software.

"documented" in your wording means that this behaviour of Xilinx software was documented for the user of the software or that it internally uses it?

oh well if it that info has been available earlier I have missed it (I am not so good doing that RTFM thing sometimes)

and sure the last picosends do count also!

Antti

Antti, The numbers for the LUT delay differences from the various inputs are not in the data sheet, but they are (and have been for years) in the speeds files used by the software, and are (and have been) thus also reported in any performance reports. Regarding the DSP columns, I do not know where you read the number 10 (please tell me so we can fix that mistake). Far more relevant is the number of such slices, and the max is 192 in the 5VLX330.

Peter Alfke

ug193 page 13

"Virtex-5 family members have one, two, six, or ten DSP48E columns."

Antti, that's what happens when we release a family in several installments. As you can imagine, there will be an "SX" subfamily, and it will have more DSP columns, up to ten. Now you guys know one more deep secret... Peter Alfke

I did guess that actually. Well the logic in SX doesnt scale with the DSP columns, but still it will be heavy crunching engine :)

Antti

We are currently planning on the V4 SX55, but really could use more speed, pins, MACs and less power. Looks like the speed increases slightly, possibly more with the rearranged MAC; the power is down, that's good; will there be an increase in the MACs and pins available? Any indication of a release date for samples? Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive Optics