Virtex 5 announced

Marc,

Please contact your local Xilinx FAE.

You might be a good candidate for early access.

Aust> We are currently planning on the V4 SX55, but really could use more speed,

Ok, you asked for it, so here goes:

Tsk, tsk, tsk... how could you let Altera get ahead of you this way...

;-)

Congrats on the new babies. They look good!

Best regards,

Ben

Ben,

Thanks.

And, yes, it was painful to trip on V4 FX, but we still beat them with a gigabit transceiver for 90nm....just not by the six months we had intended to originally.

Aust> Aust>

Perhaps *a* gigabit... but certainly not 6, nor a robust 3 :-)

Sorry, couldn't resist.

- Paul

hm to my understanding the V4 MGT are stripped down from original spec (10G) to meat the serdes in Stratix-IIGX ? So where do the V4 serdes beat SII-GX ? Perhaps they do, but for me it's not so obvious (not since the virtex 10G rocketio is "taken out" from V2Pro-X and V4).

Paul, I assume Cyclone-III, Stratix-III, MAX3 products will come H1 2007, (based on Altera claim that 65nm Altera products are announed late

2006) - I wonder if Altera will get the 65nm products (some) out this year? If we can expect the announcement, then I would assume Altera would claim their 65nm being shipped at the time of the press release (late 2006?)

Hi Antti,

I cannot comment on announcement or release timeframes for our next-gen product family/families. But I'm sure you didn't expect me to answer your question :-)

All I can tell you is that our next-gen products will be pretty cool.

Regards,

- Paul

well, yes-no ;) the info about Altera 65nm press coming out this year (end of) is directly from Altera (not from rep or disti), so if that info is out-dated, e.g. if the Altera 65nm PR is either coming way earlier or way later, than on that topic you may have responded. no comment means that the assumption (end of 2006) could still be consider best guess ?

Antti PS hope you guy fixup the mockup with MAX2, I mean machXO beats MAX2 hands down, not that MAX2 is bad, it's pretty nice, but.. no RAM is a real issue

Hi Antti,

No comment means that we could be coming out any time.

Max II is pretty awesome in many ways (performance, cost per logic function, etc.). There are some applications where non-volatility and RAM would be handy, and these aren't addressed by Max II. We've got that feedback and will factor it into future architecture decisions -- but its always a trade-off of the cost (die-size impact) of adding additional features vs. the size of the market that those additional features will open to us.

Regards,

- Paul

Antti,

The heat is really on now. Since we announced the LX50, LX85 and LX110, all sampling (and already sampled), the heat up on North 1st Street has got to be intense.

"No comment" could also mean "Oh Crud!"

Three days, 5 hours since V5, and counting .....

Tick, tick, tick, tick ....

No pressure, really. Take your time.

Tick, tick, tick, tick ....

Aust> Hi Antti,

Yes, cost/FF is ok, but the 'cost/size of the smallest device' have taken quite a hike with this family. So it missed quite a large chunk of 7000 and 3000 markets.

Leaves AnaChip, Atmel, Lattice, Xilinx in the low power, small package arena.

You could always just admit it was an oversight, instead of using 40 odd words to say the same thing... :)

-jg

I've missed the twists and turns of the SERDES/MGT saga.

I would be grateful if someone could briefly summarise what was promised in the various product generations and what was (eventually) provided.

WAS =================================== V2Pro-X (highest speed grade only!) - 10GB/s V4FX - 10GB/s

REALITY =================================== V2Pro-X highes speed grade - not available any more V4 spec reduced to 6.x GB/s V5 spec also 6.x GB/s

that how I understand the "saga"

Antti

A couple of RAM banks and a PLL would make all the difference to the MaxII.

I'd also add 5V tolerant inputs, and smaller/cheaper versions to a wish list, if you making a collection.

mvh.,

David

I see today QuickLogic are ramping their PolarPro devices : Claim appx $2.95 (in the mythical 'high volume' ) for the 640 register device.

These devices DO have RAM and also FIFO controllers

So they go up against the MAX II and Mach XO, (but are, of course, OTP - what you gain is low static Icc)

Still you could develop using MachXO and then consider a move to PolarPro, if the Lattice devices are too hungry, or too expensive... ?

-jg

Looks great for low-power applications! But I was surprised to be completely unable to find a list of their distributors on the QuickLogic web site. How do they expect to sell any parts?

Any idea of the cost of the development software?

It was also unclear to me whether the parts can be programmed in-circuit (though of course only once), or whether they have to be programmed by a standalone programmer before they are soldered down.

Well, it isn't exactly free. You do take a hit in the LUT performance, which as you point out is actually a win *IF* the design would have gone to two levels of logic with only a 4-LUT. The fact of the matter is, as a high performance system designer, I specifically design my logic so that it has only one layer of logic between FF's. With that in mind, then assuming all else is equal, the 6-LUT represents a decrease in absolute clock performance. In the case of V5, that hit is hidden with the gain associated with the smaller geometry, and also as I recall some of the inputs to the 6-LUT are significantly faster than other inputs.

Am I complaining? No, not really. If I were to complain, it would be more about the new architecture making my existing library pretty much obsolete.

Marc,

The big win you'll see is that the V5 carry chain is fast enough to keep up with the DSP48E's, where in V4, the fabric carry chain speed is dismal compared to the speed of the DSP48's. You'll have to get an NDA with Xilinx to get the details on planned V5SX devices.

Why do we change SW everytime a new device comes out? every 6 months? Why can't have just a service pack...?

Unhappy sw user

Mr. Andraka (and others),

I am curious as to how you specify a single logic-layer in these high-speed designs. Do you explicitly specify the individual LUTs in an HDL, or can you code at a higher level and synthesize down to single-layer logic between flops?

Thank you, Stephen Craven