Hello all,
I have one question about usage of LUT and Registers in Xilinx Virtex 2 FPGA:
if, inside a slice, the LUT is consumed by some logic product, but not the corresponding register, is this register available for other use (for example, registering signal coming from an other slice) ? or is it disabled for the whole design ? does it depend on the compilation tool ?
thanks, Julien Eyries
It is available for other purposes. Look at the picture of the internals of a slice in the V2 data sheet.
If you are using less than 99% of the slices in the FPGA, map (which is responsible for assigning logic to slices) will not put unrelated LUTs and FFs into the same slice. (See the map report for the amount of "unrelated logic packing".) This explains why you can keep adding logic to your design, but the slice utilisation stays at 99%. Map tries to avoid unrelated logic packing because this tends to make the later placement pass much more difficult.
Does this waste slices? Sure, but what else are you going to do with them?
Regards, Allan.
Allan,
thank you for your explanation ; now i will have no more regret to use all those registers !
Julien .
Heh yeah, registers are "free." If your design can handle the register delays, use them as often as you can, it'll make your routing easier. I throw in registers without thinking about it. I'm sure if I ever work for an ASIC company, I'll have to unlearn that habit.
Also the LUTs can be used as 1-bit wide shift registers that can be 1-16 "registers" deep. They're called SRL16s. Very handy for adding delay to signals to make them line up with other signals, clock cycle wise.
Regards, Vinh
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