Hello all,
I have one question about usage of LUT and Registers in Xilinx Virtex 2 FPGA:
if, inside a slice, the LUT is consumed by some logic product, but not the corresponding register, is this register available for other use (for example, registering signal coming from an other slice) ? or is it disabled for the whole design ? does it depend on the compilation tool ?
thanks, Julien Eyries