altough brand new I hope someone already made some experience with Virtex-5. I just switched from Virtex-4 to Virtex-5 and I must admit that the clock managment is... and remains... somewhat unclear to me!
It's plain to see that the clock management is handled a bit differently than Virtex-4. Virtex-5 clocking uses both DCM (digital clock managers) technology for delay control and PLL (phased lock loop) technology for lower jitter clock generation. But what does that mean to me, practically? What should I account for when designing a PCB with Virtex-5? Which IOs am I supposed to use?
In Virtex-4 I had Global Clock and Regional Clock Inputs. So far so good. In Virtex-5 I have plenty of different clock inputs and it is almost impossible to arrange for an optimal clock management at the time prior to developing the internal VHDL logic for the FPGA. Basically I'd like to know how to connect my global clock sources to the FPGA without catching problems later in implementing the VHDL and getting confronted with timing errors, etc.
Same problem - still much worse - with the RocketIO reference clocks! Plenty of clock inputs but. much too confusing! For example I'd like to take one reference clock for an arrangement of 10 RocketIOs. No problem with Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 for the clocks can only supply 4 RocketIOs at once... as far as I can judge.
Still, I may be wrong! So any help is highly appreciated.