Spartan 3 - Internal busses & tristate ?

Yes, MUXs are the way to go. However, you can still use tri-state values in your VHDL code ('Z') and the synthesizer will implement the resolution as MUXs. I remeber a discussion where one guy believed that there must be tri-state buses inside the FPGA (there where never TS buses in Altera FPGAs) because he used the 'Z' values in his code (synthesizers are smart).

That coding style can save you a lot of code and keeps things modular. I'm using it for an internal IO-subsystem bus.

Martin

---------------------------------------------- JOP - a Java Processor core for FPGAs:

slave.

masters

request

I've put my multiple reads through a series of OR gates. Rather than using a multiplexer which allups up to 2 elements per logic cell in one structure, I use gated results - two per LUT - where these LUTs can be located closer to the sources, potentially making routing a little easier. While I register this first stage, many designs may not have that luxury. A wide OR of all those gated results comes down to a very nice logic tree to get low delays through standard logic without having to consider the issues around a mux. Do multiplexers do a good job when there are a number of unpopulated nodes on the MUX tree? A wide OR doesn't care.

There is a little extra time to generate the gate signals from the address where the time would be more or less free in a MUX but I have the address before I have my read data qualified (I'm not on the PCI bus, myself) so the initial decodes aren't a big timing hit. These gates are the same signals that would be used for an internal tristate anyway, so if you have an existing tristate-driven design, it should be simple and timely to change it to a wide OR of gated signals.

Look at teh wishbone bus spec on

Eric