It is unclear on what you mean by powering the "configuration block" to
3.3V. You can power Vcco_0 (aka Vcco_config) to 3.3V. Be sure to read the V4 Configuration UG (see pg 15) on the requirements for all the dedicated configuration input pins and other requirements based on your configuration mode.
Just had a look at some of the Xilinx development boards e.g. ML405 an they seem to have Vcco_0 connected to 3.3V but have the pullups on done init_b connected to 2.5V. Is it possible to have them pulled up to 3.3 instead? The documentation seems a bit vague about what supply you need t use.
I found where we have some info on mixed voltage environments in the config section of the Virtex-II UG
(see pg 281) While this is not a V4 Users Guide and your issue is not specific to the JTAG pins, the information is applicable to your device. The main point to keep in mind is that the Vih-min for LVCMOS33 is 2.0V. At 2.5V on the pull-ups for DONE and INIT, you exceed this by ~500mV and are OK (assuming no SI issues in the PCB). This may explain the mixed voltages on the ML405.
If you have Vcco_0 at 3.3V the configuration pins are expecting LVCMOS33 levels, thus there is no problem with having the pull-up Vcc to DONE and INIT at 3.3V.