Virtex-4 CCLK termination

Hello all,

I am new to this group, but it has already been a great resource.. thanks to all who post advice and suggestions! Good stuff.

My current issue involves the Virtex-4 configuration pin called CCLK, which according to the V-4 Configuration Guide, "is different from previous Xilinx FPGAs" and requires parallel Thevenin termination. Basically, a 50 ohm resistor pulled up to Vcco/2, OR a 100 ohm pulled up to Vcco and a 100 ohm pulled down to GND. Two questions:

1) Is this REALLY necessary, or just a good thing to have when configuring a device at higher CCLK frequencies? What if I just clock the bitstream at, say, 1 MHz?

2) What should I do since I want to have the option of using both Master Serial and Slave Serial? The CCLK signal will potentially terminate at either side, so where should the termination resistor(s) be placed?

Thanks in advance,

-mike.

Reply to
shogmic
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Mike,

Frequency does not matter. It is all about rise time.

A fast rise time will create reflections. Reflections will create multiple edges. Multiple edges will cause double clocking. Double clocking will cause the device to be confused, and not configure.

If you simulate the entire trace for CCLK, with the actual dimensions, and impedances, and loads and drivers (such as using Mentor's Hyperlynx SI tool), you will see what I am referring to.

Also, if you simulate the run, you may find how to do this without a termination.

It is so much simpler if we just tell you to do this as a best practice, rather than require you to simulate the trace, and design the net such that it has no reflections.

Typically CCLK runs to many devices, so making such a net have no reflections is not possible without a parallel termination at the end of the run.

Aust> Hello all,

Reply to
Austin Lesea

I would suggest doing whatever they say. I have had trouble designing a Spartan board downloading at 5Mhz. Adding the resistors helped quite a bit but still I have some flyby taps at about 10mm that still give me trouble. It also helps if you can turn off the other clocks during your download periods.

Don't know about your master/slave problem. Perhaps you can add a series resistance and get by with that as, as you say, you want to clock at 1 MHz.

Reply to
Brad Smallridge

Reply to
Peter Alfke

Wow, I'm so relieved to see that someone else has done this. The real trick, however, is to make sure that this hack works long enough, in production, so that your stock options are vested, exercised, and sold.

I guess it's safe for me to come out-of-the-closet, now. Thanks for your honesty, Peter.

Bob

Reply to
Bob

My suggestion is like a band-aid or an aspirin. Perhaps effective, but really just camouflaging the true problem. The true problem is improper lay-out or wrong termination, generating double-pulses from the fast transitions. The CCLK frequency itself is irrelevant. Peter Alfke

Reply to
Peter Alfke

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