Hello all,
I am new to this group, but it has already been a great resource.. thanks to all who post advice and suggestions! Good stuff.
My current issue involves the Virtex-4 configuration pin called CCLK, which according to the V-4 Configuration Guide, "is different from previous Xilinx FPGAs" and requires parallel Thevenin termination. Basically, a 50 ohm resistor pulled up to Vcco/2, OR a 100 ohm pulled up to Vcco and a 100 ohm pulled down to GND. Two questions:
1) Is this REALLY necessary, or just a good thing to have when configuring a device at higher CCLK frequencies? What if I just clock the bitstream at, say, 1 MHz?2) What should I do since I want to have the option of using both Master Serial and Slave Serial? The CCLK signal will potentially terminate at either side, so where should the termination resistor(s) be placed?
Thanks in advance,
-mike.