simprim errors

I generate a testbench and then do Simulate Post-Translate VHDL Model in ISE 6.2.03i. Modelsim frowns as follow:

# ** Error: (vcom-19) Failed to access library 'simprim' at "simprim". # No such file or directory. (errno = ENOENT) # ** Error: rcvr_translate.vhd(18): Library simprim not found. # ** Error: rcvr_translate.vhd(19): Unknown identifier 'simprim'. # ** Error: rcvr_translate.vhd(20): Unknown identifier 'simprim'. # ** Error: rcvr_translate.vhd(22): VHDL Compiler exiting # ** Error: C:/Modeltech_5.8d/win32/vcom failed.

I have compiled both simprim and unisim libraries in $Xilinx directory. The testbench includes the following headers:


I like to do post translate/map/PAR timing simulation if I could only get pass this error.



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Yaseen Zaidi
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Check the mapping 'vmap' command which makes the association between actual simprim library and directory/path where it is stored. There issomething wrong there, typical error if you received a Modelsim Macro (.do file) exemple : vmap simprim C:/Xilinx/vhdl/mti_se/simprim or vmap simprim C:/Modeltech_xe_starter_5.7/xilinx/vhdl/simprim

note the '/' instead of '' in pathnames becauseModelsim is build upon tCL

"Yaseen Zaidi" a écrit dans le message de news:

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Looking at the notes of an old training course, it says compile the following source file in the following order:

simprim_Vpackage.vhd simprim_Vcomponents.vhd simprim_VITAL.vhd

Perhaps changing the order and adding VITAL may help.

Regards, Jock

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I believe that you need to map the simprim library name to where you compiled the simprim models. There are many ways to do this. One way is go to the modelsim.ini that your design process is using. It may be in a project specific path, or a global one. I do not know what method you are using. In modelsim.ini, under [library] add : simprim = "your path name"

e.g. simprim = G:/ModelsimLibs/xilinx6_2sp3_PE8_3c/simprim

Hope this helps.


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Insert this command line in the xyz_vhd_tb.ndo file generated after pressing generate post translate model.

compxlib -s mti_se -f all:s -l vhdl -o /home/saurabhc/check (last one is the path of directory having VHDL files)

if this command is added then there is no need to add this line in post map file.

for more info about this line write compxlib -help in the command prompt in ur modelsim tool. bye Saurabh

Reply to
Saurabh Chhabra

hi ..

  1. create a simprim libraray in ur proj with >>> vlib simprim
  2. map simprim to the destination directory >>

vmap simprim destination.

  1. then compile the design. >> project compileall
  2. then simulate with simprim library and sdf file.

but prior to step 1 compile all vhdl/verilog source files to simprim library. (this can be differenr project)depending on what backannoneted netlist you generate.


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