I generate a testbench and then do Simulate Post-Translate VHDL Model in ISE 6.2.03i. Modelsim frowns as follow:
# ** Error: (vcom-19) Failed to access library 'simprim' at "simprim". # No such file or directory. (errno = ENOENT) # ** Error: rcvr_translate.vhd(18): Library simprim not found. # ** Error: rcvr_translate.vhd(19): Unknown identifier 'simprim'. # ** Error: rcvr_translate.vhd(20): Unknown identifier 'simprim'. # ** Error: rcvr_translate.vhd(22): VHDL Compiler exiting # ** Error: C:/Modeltech_5.8d/win32/vcom failed.
I have compiled both simprim and unisim libraries in $Xilinx directory. The testbench includes the following headers:
library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL;
I like to do post translate/map/PAR timing simulation if I could only get pass this error.
Thanks,
YZ