This group is of real help to people that really need help and assistance during the course of designing and programning. Well, all these while i was into desiging and development. now i have been shifted to VERIFICATION and TESTING in VHDL. i have done verification earlier in TESTBENCHES, wrote a code and given input vectors and verified the output vectors. Is this basically how testing is done, or lots more into it. I'am just aware of this way of testing of the VHDL code in TESTBENCHES. If there are many other ways of testing and validation which i'am unaware of PLEASE let me know.
I'am refering a book:
Writing Testbenches: Functional Verification of HDL Models, Second Edition by Janick Bergeron.
well its just the begening. Can i please be informed of sites or pdf doc that will help me gain more knowledge in this.
Along with this i request to get info, ideas on the importance, advantages, of testing, diffrent tools used in verification.
One last doubt, in verification, do we even work on STATIC TIME ANALYSIS and SYNTHESIS. or this is done by the designer itself..
would be very thankful to get replies soon.