VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?

Martin,

If your signal "counter" is declared as an integer with a valid range you can then use a reset as shown:

signal counter : integer range 0 to 67108863 := 0; ... if reset = '0' then signal counter Hello,

Allan & Jason B. show the typical ways; alternatively, if you are using numeric_std, you could write:

counter

Personally, if I'm doing a counter I would use an unsigned type (or even an integer!) rather than "casting" to std_logic_vector all the time. After all, what you're representing is a number...

Cheers, Martin

Hi,

Here's a different but similar question: Is there a better way to do the following (vector extension):

signal A,B: std_logic_vector(10 downto 0); signal X: std_logic_vector( 7 downto 0);

A Jason T. Wright

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759