I have never done an FPGA design and I am considering purchasing the Starter Board. It has crossed my mind to implement at least part of a design I did in an ASIC many years ago. The largest part of the ASIC design was a "funnel" shifter. Basically the shifter operated as a barrel shifter on the 96-bit input and output the 21-bits beginning at any designated position. Cycle time was one clock.
Is this doable with the XC3500 on the Starter Board? How much of the logic would this consume? Any thoughts on what the max clock rate would be?