hii
i have to study TCL SCRIPTING and i have to verify the VHDL codes, i have learnt this lannguage but have to verify the vhdl code using TCL SCRIPT. can any one out here please tell me how to go about. Any link or pdf doc. that explains how to do the same. suppose i have to verify a counter. i have to force values to teh signal, get it on the waveform. the entire process that a testbench does, has to be performed in TCL SCRIPT... i hope query is well explained.
thanks HAPPY NEW YEAR TO ALL
If you have access to Modelsim then have a look in the Command Reference manual. Look for the force, change, examine and when commands, all have some simple examples.
Hans
hii... i'am using modelsim PE. you saying its a command line interface, are there any commands as such
that interfaes directly with the vhdl file, suppose the vhdl file that has to be verified is d_ff.vhd. should i even have the testbench file along with this or just need the d_ff.vhd file. and now to interface the script with this ie.. with the vhdl file what should be done. should any command be used in vsim. how can i force values to the signals, view the wave form using the command add wave. can you plzz help me, as in my company i should learn this on my own, i'am a trainee and have to get this concept clear soon. can u please give me a example using a D Flip-Flop.
it would be great n really appreciated if you help me out..
Thanks..
thanks Hans
A Very "Happy New Year 2006" to you & your family!!! May this year bring in Peace, Happiness, Prosperity & Good health!!!!
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