The planned architecture: telephone line -> ADCs (8k samples pre second)-> FPGA (samples into ram) -> AXIS controller (with Ethernet)
The goal is to tap several (about 8) telephone channels and convert them into TCP/IP stream. TCP server will run on Axis controller. I consider to use FPGA for polling ADCs and storing samples into Block RAM. When FPGA buffers are say 50% full, the FPGA would interrupt the controller. AXIS runs at 100MHz. The interrupted controller would address FPGA by address bus and reads all samples from FPGA memory. I think 1 kbyte sample buffer would be enaught for an audio channel.
I'm new to this filed and want to ask whether the architecture choosen is feasible? Which FPGA families suit better for the task?
AXIS is a risk processor; I'm thinking to implement addressing scheme where there is an address for each audio channel. That is, any two sequential reads from the same address would read two sequential samples from FPGA. It it normal solution?
Thanks, any references are highly appretiated!