2066-pin processors

It's all down to the division of labour in pin production. Adam Smith's law posits that the number of pins doubles about every two years.

Cheers

--
Clive

I have a good picture demonstrating that. Somewhere!

NT

3647 pins!

Pere

Clive Arthur wrote in news:pvfn5r$nf1$ snipped-for-privacy@dont-email.me:

No. The number of transistor elements. The number of pins does not nor did not follow that rule. It jumped in spurts. Chip packages did not always use all of the pins of a given form factor either.

Support chips (chipsets) also weigh in to this. Math-COs used to be a separate chip and are now fully integrated, as are everal other previously external segments of what makes up a computing platform.

LOL!

LGA 3647 "up to six DDR4 channels" LGA 4189 "8-channel DDR4, up to 230W"

--
 Thanks, 
    - Win

It is time to rethink microprocessor architecture. Put several gigabytes of memory on the processor chip. Call it "cache", if you do not want call it main memory. Alternatively stack RAM chips upon each other on to the same chip carrier as the core to minimize distances and hence propagation delays.

If each pin has a few pF stray capacitance and the pins are operated at 100+ MHz, a huge amount power is lost just charging and discharging the pin stray capacitances.

LGA 4189 is Intel's Ice Lake Xeon for those playing along at home.

Cheers

cool, are you going to use wire wrap?

--

John Devereux

I hadn't found that one yet. AMD's sockets SP3 and TR4 for the Epyc and Threadripper are 4094 pins. There are a number of FPGA's at around 3000 pins, and Power9 processors have 3899 pins. I'd expect the Power10 to be bigger, and some of the SPARC processors must surely have vast pin counts.

One is reminded of the Signetics WOM chip datasheet, with its graph of number of socket insertions v number of pins remaining...

Somewhere out there there's a pic of a Russian chip way way bigger, with bunch after bunch after bunch of wires hanging off it. I just couldn't find it.

NT

Did you lay out and build your own CPU board?

What OS? Bios?

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

John Larkin wrote in news: snipped-for-privacy@4ax.com:

There are plenty of LGA 2066 MOBOs out there.

At this level, homespun would very likely be a major step backwards.

I'll take what the pros have been designing and familiarizing themselves with for years over even the most advanced, knowledgeable engineer doing one on his own. There are way to many places to get fouled up. Looking at even the best motherboards, one sees squggly litle traces meant to adjust physical arrival time of a signal. A design needs a lot of testing and very few get made from the first layout iteration.

Winfield Hill wrote in news: snipped-for-privacy@drn.newsguy.com:

Just think how difficult things would be if we were still using pin grid array.

The insertion force... the extraction force! Wow.

I do not know what my Xeon is. It is a mobile machine, so it is likely hard soldered no?

The 4004 was only 16 pins.

8 bit CPU Pins Year 8008 18 1971 8088 40 1972 8085 40 1976 16 bit CPU Pins Year 8086 40 1976 8088 40 1979 80186 68 1982 80286 68 1982

32 bit 80386 132 1985 80486 196 1989 80586(P5) 273-321 1993 P6 387 1995 Pentium II 242 1997 PII Xeon 330 1998 PIII Xeon 603 1999

Martin Riddle wrote in news: snipped-for-privacy@4ax.com:

home.

It was for supercomputers and single die "cloud computer" use.

Not likely see it ever in a consumer box. It was started back in

2006, but the "Ice Lake" currently being referred to is a 10nm process not even being done yet in mass production.

I'll take one of the 14 core jobs.

snipped-for-privacy@downunder.com wrote in news: snipped-for-privacy@4ax.com:

Each 'pin' of a PGA does (perhaps).

Each 'contact pad' of an LGA socketed device does not.

They went from PGA to LGA specifically to negate (read reduce) this effect as contact counts increased.

Not really. The voltages are small, under 1V*. They do toggle on the order of 1GHz (or more, for the CPUs we're talking about here). The pins and traces are certainly more than "few pF", but that's alright because they are transmission line structures. (Which means you still burn at least as much power as the equivalent capacitance gives, up to a maximum of the transmission line impedance.)

*Actually I forget if they're using LVDS or SSTL or what these days. SSTL-style sigalling is actually ~"CMOS with extra steps": there's a VREF (VDD/2) ground plane instead of differential pairs, the transmitters are basically CMOS as far as I can tell, and the receivers are differential with a few timing tweaks. The transmitters may also have preshoot, I don't know.

AFAIK, PCIe does come off the CPU (what used to be the "Northbridge" is fully integrated: all the caches, DRAM controller, bus interfaces, and probably a lot of system monitoring devices too), so there will be LVDS pairs for that of course.

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Design 
Website: https://www.seventransistorlabs.com/

And put 256 ARM or RISC-V cores on there. Then write a new OS.

Clean restart.

3.3 volts, 5 pF, about 20 watts if all are slamming at 100 MHz.

LVDS, a lot less.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com