use of attributes

Dear Dr VHDL I am a newbie struggling with an exercise to write a parameterised model of a PCB containg memory ICs. The answer (yes I peeked at the book but I wish I hadn't) contains this code fragment -

subtype word is std_logic_vector(wordsize-1 downto 0) ; type mem is array(0 to 2**addresssize-1) of word ; variable memory: mem := (others=>word'(others=>'U')) ;

Why does the above define a type from a subtype ? Is this cos VHDL doesn't allow subtypes of subtypes ?

And more important -

What does line 3 mean by (others=>word'(others=>'U')) ?.

I understand stuff like (others=> 'U') but what sort of ?attribute of word is word'(others=>'U'))

thanx John.

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Pears772
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Yup, this one should have gone to comp.lang.vhdl.

"type mem" is a completely new data type (an array of a particular size of std_logic_vector) that has never been seen before in this compilation; that's why it needs the "type" keyword. By contrast, "subtype word" is just a particular version of the existing type std_logic_vector. Since it starts from the existing definition of std_logic_vector and then constrains it by specifying a specific subscript range, it's a subtype.

No, it's because you're defining something new.

In any case it's not strictly true that "VHDL doesn't allow subtypes of subtypes" because you can do this...

subtype SHORT is integer range -32768 to 32767; subtype BYTE is SHORT range -128 to 127;

although you are partly right - you cannot make a new subtype by further constraining the subscript range on your subtype "word".

It's not an attribute. The syntax typename'(expression) is known as "type qualification" and it specifies that the expression must be interpreted as being of the specified type. It's useful if there is any ambiguity. I am fairly sure that it's unnecessary in your example, because the whole expression (others => (others => 'U')) is known to be of type "mem", so its elements are known to be std_logic_vector(wordsize-1 downto 0), so there is no ambiguity in the interpretation of (others=>'U'). However, a type qualification like this is ALWAYS harmless, as it can't possibly change anything - the expression must already be a legal value of the specified type; no conversion takes place.

One very common use of type qualification is in creating fixed messages to an output stream:

variable L: line; file F: ....

...

write (L, string'("Title message")); writeline(F, L);

The write() procedure is overloaded so that it can do...

write(L, string) write(L, bit_vector)

Without the string'() type qualification, the VHDL compiler would be confused because a bunch of characters inside string quotes might also be a bit_vector. (Yes, you and I know that a bit_vector can't have anything other than 0 and 1 in it. But the compiler doesn't want to make guesses about the string's contents.)

HTH

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Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Jonathan Bromley

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