USB2.0

Hello,

I am trying to interface a USB receiver chip with the FPGA. The USB chip can only allow unidirection communications. it just outputs eight bit of data at 12 MHz at each rising edge of the USB clock in brust mode. The scheme I used is simple but my State machine is getting lost and screwing up the count of the counter. some times It works sometimes it does not work! I am using the counter to generate addressess for the Dual port RAM. My VHDL comlplier also ignoring the intialization of the signal Flag1 and I do not know why? The FPGA is running at the clock frequency of 60MHZ.

Thanks very much. Regards john

signal State : unsigned(7 downto 0); signal nextstate : unsigned(7 downto 0); constant E0 : unsigned(7 downto 0):="00000000"; constant E1 : unsigned(7 downto 0):="00000001"; constant E2 : unsigned(7 downto 0):="00000010"; constant E3 : unsigned(7 downto 0):="00000011";

Signal State1 : unsigned(7 downto 0); Signal nextstate1 : unsigned (7 downto 0); constant F0: unsigned(7 downto 0):="00000000"; constant F1: unsigned(7 downto 0):="00000001";

Signal inc: std_logic:='0'; Signal eq_signal : std_logic:='1'; Signal Reset_A : std_logic; Signal counter_clock : std_logic;

Signal USB_port : unsigned ( 7 downto 0); Signal Flag1 : std_logic:='0';

Begin

Data_Bus Flag1

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john
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Reply to
Symon

So how exactly are you moving the USB data available status and the data from the 12MHz clock domain to the 60MHz clock domain ????

Maybe go read this:

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Including the links at the end of the article.

Philip

Philip Freidin Fliptronics

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Philip Freidin

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